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pr el i m i nar y data sheet v0.7 2015-10 microcontrollers xmc4700 / xmc4800 microcontroller series for industrial applications xmc4000 family arm ? cortex ? -m4 32-bit processor core
edition 2015-10 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infi neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-suppo rt devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
pr el i m i nar y data sheet v0.7 2015-10 microcontrollers xmc4700 / xmc4800 microcontroller series for industrial applications xmc4000 family arm ? cortex ? -m4 32-bit processor core
xmc4700 / xmc4800 xmc4000 family preliminary data sheet v0.7, 2015-10 trademarks c166?, tricore?, xmc? and dave? are trademarks of infineon technologies ag. arm ? , arm powered ? , cortex ? and amba ? are registered trademarks of arm, limited. coresight?, etm?, embedded trace macrocell?, embedded trace buffer? and thumb ? are trademarks of arm, limited. synopsys? is a trademark of synopsys, inc. xmc4[78]00 data sheet revision history: v0.7 2015-10 previous versions: v0.6 2015-06 page subjects 15 devices with es-aa markings covere d with the same ids as the ees-aa markings. 19 , 20 , 21 , 22 updated pin configuration drawings and package pin summary table with swapped rtc_xtal pins. 64 corrected parameter name of usb pull device (upstream port receiving) definition according to usb standard (referenced to dm instead of dp). 70 updated some power consumption values. 127 updated package outline drawing of pg-lqfp-100-25. we listen to your comments is there any information in this document that you feel is wrong, unclear or missing? your feedback will help us to continuousl y improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family table of contents preliminary data sheet 5 v0.7, 2015-10 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 device type features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 definition of feature variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 package pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 port i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.2.1 port i/o function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 power connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.1 parameter interpretati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.3 pin reliability in overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4 pad driver and pad classes summary . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.1 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.2 analog to digital converters (vadc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.3 digital to analog converters (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.4 out-of-range comparator (orc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2.5 die temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2.6 usb otg interface dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.7 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.2.8 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.2.9 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.3.2 power-up and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.3.3 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.3.4 phase locked loop (pll) characteristics . . . . . . . . . . . . . . . . . . . . . . 78 3.3.5 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.3.6 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.3.7 serial wire debug port (sw-dp) timing . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.8 embedded trace macro cell (etm) timing . . . . . . . . . . . . . . . . . . . . . 84 3.3.9 peripheral timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table of contents subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family table of contents preliminary data sheet 6 v0.7, 2015-10 3.3.9.1 delta-sigma demodulator digital interf ace timing . . . . . . . . . . . . . . 85 3.3.9.2 synchronous serial interface (usic ssc) timing . . . . . . . . . . . . . . 86 3.3.9.3 inter-ic (iic) interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.3.9.4 inter-ic sound (iis) interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.3.9.5 sdmmc interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.3.10 ebu timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.3.10.1 ebu asynchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.3.10.2 ebu burst mode access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.3.10.3 ebu arbitration signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.3.10.4 ebu sdram access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.3.11 usb interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.3.12 ethernet interface (eth) characteristics . . . . . . . . . . . . . . . . . . . . . . . 116 3.3.12.1 eth measurement reference points . . . . . . . . . . . . . . . . . . . . . . . 116 3.3.12.2 eth management signal parameters (eth_mdc, eth_mdio) . . 117 3.3.12.3 eth mii parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.3.12.4 eth rmii parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.3.13 ethercat (ecat) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.3.13.1 ecat measurement reference points . . . . . . . . . . . . . . . . . . . . . . 120 3.3.13.2 eth management signal parameters (mclk, mdio) . . . . . . . . . . 120 3.3.13.3 mii timing tx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.3.13.4 mii timing rx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.3.13.5 sync/latch timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.1.1 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.2 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family about this document preliminary data sheet 7 v0.7, 2015-10 about this document this data sheet is addressed to embedded hardware and software developers. it provides the reader with detailed description s about the ordering designations, available features, electrical and physical characte ristics of the xmc4[78]00 series devices. the document describes the characteristi cs of a superset of the xmc4[78]00 series devices. for simplicity, the various device types are referred to by the collective term xmc4[78]00 throughout this manual. xmc4000 family user documentation the set of user documentation includes: ? reference manual ? decribes the functionality of the superset of devices. ? data sheets ? list the complete ordering designations, available features and electrical characteristics of derivative devices. ? errata sheets ? list deviations from the specifications given in the related reference manual or data sheets. errata sheets are provided for the superset of devices. attention: please consult all parts of the documentation set to attain consolidated knowledge about your device. application related guidance is provided by users guides and application notes . please refer to http://www.infineon.com/xmc4000 to get access to the latest versions of those documents. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 8 v0.7, 2015-10 1 summary of features the xmc4[78]00 devices are members of the xmc4000 family of microcontrollers based on the arm cortex-m4 processor core. the xmc4000 is a family of high performance and energy efficient microcontr ollers optimized for in dustrial connectivity, industrial control, power c onversion, sense & control. figure 1 system block diagram cpu subsystem ?cpu core ? high performance 32-bit arm cortex-m4 cpu ? 16-bit and 32-bit thumb2 instruction set ? dsp/mac instructions ? system timer (systick) fo r operating system support ? floating point unit ? memory protection unit ? nested vectored interrupt controller ? general purpose dma with up-to channels ? event request unit (eru) for programmab le processing of external and internal service requests ? flexible crc engine (fce) for multiple bit e rror detection pmu rom & flash bus matrix cpu arm cortex-m4 dsram1 ebu dsram2 psram fce gpdma0 gpdma1 usb otg ethernet dcode system icode peripherals 0 peripherals 1 pba0 data code wdt rtc eru0 scu eru1 vadc posif0 ccu40 ccu41 ccu42 usic0 dsd posif1 ccu80 ccu81 ledts0 ccu43 ports dac sdmmc usic2 usic1 multican system masters system slaves pba1 ethercat subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 9 v0.7, 2015-10 on-chip memories ? 16 kb on-chip boot rom ? 96 kb on-chip high-speed program memory ? 128 kb on-chip high speed data memory ? 128 kb on-chip high-speed communication memory ? 2,048 kb on-chip flash memory with 8 kb instruction cache communication peripherals ? ethernet mac module capable of 10/100 mbit/s transfer rates ? ethercatslave interface capable of 100 mb it/s transfer rates with 2 mii ports, 6 fieldbus memory management units (fmmu), 6 sync manager, 64 bit distributed clocks ? universal serial bus, usb 2.0 host, full-speed otg, with integrated phy ? controller area network interface (mult ican), full-can/basic-can with 6 nodes, 256 message objects (mo), data rate up to 1 mbaud ? six universal serial interface channels (usic),providing 6 serial channels, usable as uart, double-spi, quad-spi, ii c, iis and lin interfaces ? led and touch-sense controller (ledts) for human-machine interface ? sd and multi-media card interface (s dmmc) for data storage memory cards ? external bus interface unit (ebu) enabl ing communication with external memories and off-chip peripherals analog frontend peripherals ? four analog-digital converters (vadc) of 12-bit resolution, 8 channels each, with input out-of-range comparators ? delta sigma demodulator with four channels, digital input stage for a/d signal conversion ? digital-analog converter (dac) with two channels of 12-bit resolution industrial control peripherals ? two capture/compare units 8 (ccu8) for motor control and power conversion ? four capture/compare units 4 (ccu4) for use as general purpose timers ? two position interfaces (posif) for servo motor positioning ? window watchdog timer (wdt) for safety sensitive applications ? die temperature sensor (dts) ? real time clock module with alarm support ? system control unit (scu) for system configuration and control input/output lines ? programmable port driver control module (ports) ? individual bit addressability subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 10 v0.7, 2015-10 ? tri-stated in input mode ? push/pull or open drain output mode ? boundary scan test support over jtag interface on-chip debug support ? full support for debug features: 8 breakpoints, coresight, trace ? various interfaces: arm-jtag, swd, single wire trace 1.1 ordering information the ordering code for an infineon microcontroller provides an exact reference to a specific product. the code ?xmc4< ddd>-? identifies: ? the derivatives function set ? the package variant ?e: lfbga ?f: lqfp ?q: vqfn ? package pin count ? the temperature range: ? f: -40c to 85c ? k: -40c to 125c ? the flash memory size. for ordering codes for the xmc4[78]00 please contact your sales representative or local distributor. this document describes several derivat ives of the xmc4[78]00 series, some descriptions may not apply to a specific product. please see table 1 . for simplicity the term xmc4[78]00 is used for all derivatives throughout this document. 1.2 device types these device types are available and can be ordered through infineon?s direct and/or distribution channels. table 1 synopsis of xmc4[78]00 device types derivative 1) package flash kbytes sram kbytes xmc4700-e196x2048 pg-lfbga-196 2048 352 xmc4700-f144x2048 pg-lqfp-144 2048 352 xmc4700-f100x2048 pg-lqfp-100 2048 352 xmc4700-e196x1536 pg-lfbga-196 1536 276 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 11 v0.7, 2015-10 1.3 device type features the following table lists the avai lable features per device type. xmc4700-f144x1536 pg-lqfp-144 1536 276 xmc4700-f100x1536 pg-lqfp-100 1536 276 xmc4800-e196x2048 pg-lfbga-196 2048 352 xmc4800-f144x2048 pg-lqfp-144 2048 352 xmc4800-f100x2048 pg-lqfp-100 2048 352 xmc4800-e196x1536 pg-lfbga-196 1536 276 xmc4800-f144x1536 pg-lqfp-144 1536 276 xmc4800-f100x1536 pg-lqfp-100 1536 276 xmc4800-e196x1024 pg-lfbga-196 1024 200 xmc4800-f144x1024 pg-lqfp-144 1024 200 XMC4800-F100X1024 pg-lqfp-100 1024 200 1) x is a placeholder for the supported temperature range. table 2 features of xmc4[78]00 device types derivative 1) led ts intf. sd mmc intf. ebu intf. 2) eth intf. 3) ecat slave intf. usb intf. usic chan. multican nodes, mo xmc4700-e196x2048 1 1 sdm mr - 1 3 x 2 n[0..5] mo[0..255] xmc4700-f144x2048 1 1 sdm mr - 1 3 x 2 n[0..5] mo[0..255] xmc4700-f100x2048 1 1 m16 r - 1 3 x 2 n[0..5] mo[0..255] xmc4700-e196x1536 1 1 sdm mr - 1 3 x 2 n[0..5] mo[0..255] xmc4700-f144x1536 1 1 sdm mr - 1 3 x 2 n[0..5] mo[0..255] xmc4700-f100x1536 1 1 m16 r - 1 3 x 2 n[0..5] mo[0..255] table 1 synopsis of xmc4[78]00 device types (cont?d) derivative 1) package flash kbytes sram kbytes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 12 v0.7, 2015-10 xmc4800-e196x2048 1 1 sdm mr 2 x mii 1 3 x 2 n[0..5] mo[0..255] xmc4800-f144x2048 1 1 sdm mr 2 x mii 1 3 x 2 n[0..5] mo[0..255] xmc4800-f100x2048 1 1 m16 r 2 x mii 1 3 x 2 n[0..5] mo[0..255] xmc4800-e196x1536 1 1 sdm mr 2 x mii 1 3 x 2 n[0..5] mo[0..255] xmc4800-f144x1536 1 1 sdm mr 2 x mii 1 3 x 2 n[0..5] mo[0..255] xmc4800-f100x1536 1 1 m16 r 2 x mii 1 3 x 2 n[0..5] mo[0..255] xmc4800-e196x1024 1 1 sdm mr 2 x mii 1 3 x 2 n[0..5] mo[0..255] xmc4800-f144x1024 1 1 sdm mr 2 x mii 1 3 x 2 n[0..5] mo[0..255] XMC4800-F100X1024 1 1 m16 r 2 x mii 1 3 x 2 n[0..5] mo[0..255] 1) x is a placeholder for the supported temperature range. 2) memory types supported s=sdram, d=demux, m=mux 16-bit and 32-bit, m16=mux 16-bit 3) supported interfaces, m=mii, r=rmii. table 3 features of xmc4[78]00 device types derivative 1) adc chan. dsd chan. dac chan. ccu4 slice ccu8 slice posif intf. xmc4700-e196x2048 32 4 2 4 x 4 2 x 4 2 xmc4700-f144x2048 32 4 2 4 x 4 2 x 4 2 xmc4700-f100x2048 24 4 2 4 x 4 2 x 4 2 xmc4700-e196x1536 32 4 2 4 x 4 2 x 4 2 xmc4700-f144x1536 32 4 2 4 x 4 2 x 4 2 xmc4700-f100x1536 24 4 2 4 x 4 2 x 4 2 xmc4800-e196x2048 32 4 2 4 x 4 2 x 4 2 table 2 features of xmc4[78]00 device types (cont?d) derivative 1) led ts intf. sd mmc intf. ebu intf. 2) eth intf. 3) ecat slave intf. usb intf. usic chan. multican nodes, mo subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 13 v0.7, 2015-10 xmc4800-f144x2048 32 4 2 4 x 4 2 x 4 2 xmc4800-f100x2048 24 4 2 4 x 4 2 x 4 2 xmc4800-e196x1536 32 4 2 4 x 4 2 x 4 2 xmc4800-f144x1536 32 4 2 4 x 4 2 x 4 2 xmc4800-f100x1536 24 4 2 4 x 4 2 x 4 2 xmc4800-e196x1024 32 4 2 4 x 4 2 x 4 2 xmc4800-f144x1024 32 4 2 4 x 4 2 x 4 2 XMC4800-F100X1024 24 4 2 4 x 4 2 x 4 2 1) x is a placeholder for the supported temperature range. table 3 features of xmc4[78]00 device types (cont?d) derivative 1) adc chan. dsd chan. dac chan. ccu4 slice ccu8 slice posif intf. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 14 v0.7, 2015-10 1.4 definition of feature variants the xmc4[78]00 types are offered with seve ral memory sizes and number of available vadc channels. table 4 describes the location of the available flash memory, table 5 describes the location of the available srams, table 6 the available vadc channels. table 4 flash memory ranges total flash size cached range uncached range 1,024 kbytes 0800 0000 h ? ? ? ? ? ? table 5 sram memory ranges total sram size program sram system data sram communication data sram 200 kbytes 1ffe e000 h ? ? ? ? ? ? ? ? ? table 6 adc channels 1) 1) some pins in a package may be connected to more than one channel. for the detailed mapping see the port i/o function table. package vadc g0 vadc g1 vadc g2 vadc g3 pg-lqfp-144 pg-lfbga-196 ch0..ch7 ch0..ch7 ch0..ch7 ch0..ch7 pg-lqfp-100 ch0..ch7 ch0..ch7 ch0..ch3 ch0..ch3 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family summary of features preliminary data sheet 15 v0.7, 2015-10 1.5 identification registers the identification registers allow software to identify the marking. table 7 xmc4700 identi fication registers register name value marking scu_idchip 0004 7001 h ees-aa, es-aa jtag idcode 101d f083 h ees-aa, es-aa table 8 xmc4800 identi fication registers register name value marking scu_idchip 0004 8001 h ees-aa, es-aa jtag idcode 101d f083 h ees-aa, es-aa subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 16 v0.7, 2015-10 2 general device information this section summarizes the logic symbols and package pin configurations with a detailed list of the functional i/o mapping. 2.1 logic symbols figure 2 xmc4[78]00 logi c symbol pg-lqfp-144 port 0 16 bit port 1 16 bit port 2 16 bit port 3 16 bit port 4 8 bit port 5 12 bit port 6 7 bit v agnd (1) v aref (1) v ddp (4) jtag 3 bit tck etm / swd 5 / 1 bit v ddc (4) xtal1 xtal2 usb_dp usb_dm vbus port 14 14 bit port 15 12 bit tms porst via port pins v dda (1) rtc_xtal1 rtc_xtal2 hib_io_0 hib_io_1 v ssa (1) v bat (1) (1) v sso exp. die pad (v ss ) v ss (1) subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 17 v0.7, 2015-10 figure 3 xmc4[78]00 logi c symbol pg-lfbga-196 port 0 16 bit port 1 16 bit port 2 16 bit port 3 16 bit port 4 8 bit port 5 12 bit port 6 7bit v agnd (1) v aref (1) v ddp (3) jtag 3bit tck etm / swd 5 / 1 bit v ddc (3) xtal1 xtal2 usb_dp usb_dm vbus port 14 14 bit port 15 12 bit tms porst via port pins v dda (1) rtc_xtal1 rtc_xtal2 hib_io_0 hib_io_1 v ssa (1) v bat (1) (1) v sso v ss (8) port 7 12 bit port 8 12 bit port 9 12 bit subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 18 v0.7, 2015-10 figure 4 xmc4[78]00 logi c symbol pg-lqfp-100 port 0 13 bit port 1 16 bit port 2 13 bit port 3 7 bit port 4 2 bit port 5 4 bit v agnd (1) v aref (1) v ddp (4) jtag 3 bit tck swd 1 bit v ddc (4) xtal1 xtal2 usb_dp usb_dm vbus port 14 14 bit port 15 4 bit tms porst via port pins v dda (1) rtc_xtal1 rtc_xtal2 hib_io_0 hib_io_1 v ssa (1) v bat (1) (1) v sso exp. die pad (v ss ) v ss (1) subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 19 v0.7, 2015-10 2.2 pin configuration and definition the following figures summarize all pins, showing their locations on the four sides of the different packages. figure 5 xmc4[78]00 pg-lqfp-144 pin configuration (top view) 2 p0 . 0 1 p0 . 1 14 4 p 0 .2 14 3 p 0 .3 14 2 p 0 .4 14 1 p 0 .5 14 0 p 0 .6 12 8 p 0 .7 12 7 p 0 .8 4 p0 . 9 3 p0 . 1 0 139 p0.11 138 p0.12 137 p0.13 136 p0.14 135 p0.15 11 2 p 1 .0 11 1 p 1 .1 110 p1.2 10 9 p 1 .3 108 p1.4 107 p1.5 11 6 p 1 .6 11 5 p 1 .7 11 4 p 1 .8 11 3 p 1 .9 106 p1.10 105 p1.11 104 p1.12 103 p1.13 102 p1.14 94 p1.15 74 p2.0 73 p2.1 72 p2.2 71 p2.3 70 p2.4 69 p2.5 76 p2.6 75 p2.7 68 p2.8 67 p2.9 66 p2.10 65 p2.11 64 p2.12 63 p2.13 60 p2.14 59 p2.15 7 p3 . 0 6 p3 . 1 5 p3 . 2 13 2 p 3 .3 13 1 p 3 .4 13 0 p 3 .5 12 9 p 3 .6 14 p3 . 7 13 p3 . 8 12 p3 . 9 11 p3 . 1 0 10 p3 . 1 1 9 p3 . 1 2 8 p3 . 1 3 134 p3.14 133 p3.15 124 p4.0 123 p4.1 12 2 p 4 .2 12 1 p 4 .3 12 0 p 4 .4 11 9 p 4 .5 11 8 p 4 .6 11 7 p 4 .7 84 p5.0 83 p5.1 82 p5.2 81 p5.3 80 p5.4 79 p5.5 78 p5.6 77 p5.7 58 p5.8 57 p5.9 56 p5.10 55 p5.11 101 p6.0 100 p6.1 99 p6.2 98 p6.3 97 p6.4 96 p6.5 95 p6.6 42 p14.0 41 p14.1 40 p14.2 39 p14.3 38 p14.4 37 p14.5 36 p14.6 35 p14.7 52 p14.8 51 p14.9 34 p14.12 33 p14.13 32 p14.14 31 p14.15 30 p15.2 29 p15.3 28 p15.4 27 p15.5 26 p15.6 25 p15.7 54 p15.8 53 p15.9 50 p15.12 49 p15.13 44 p15.14 43 p15.15 16 usb_dp 15 usb _dm 21 hib_io _0 20 hib_io _1 93 tck 92 tms 91 porst 87 xtal1 88 xtal2 22 rtc_xtal2 23 rtc_xtal1 24 vbat 17 vbus 46 va r ef 45 vagnd 48 vd d a 47 vssa 19 vddc 61 vddc 90 vddc 12 5 v d d c 18 vddp 62 vd d p 86 vddp 12 6 v d d p 85 vss 89 vsso xmc4[78]00 (top view) subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 20 v0.7, 2015-10 figure 6 xmc4[78]00 pg-lfbga -196 pin configuration (top view) p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0. 11 p0. 12 p0. 13 p0.14 p0.15 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p1.8 p1.9 p1.10 p1. 11 p1. 12 p1.13 p1. 14 p1.15 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2. 10 p2. 11 p2. 12 p2. 13 p2. 14 p2.15 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.14 p3. 15 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 p5.8 p5.9 p5. 10 p5. 11 p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p7.0 p7.1 p7.2 p7.3 p7.4 p7.5 p7.6 p7.7 p7.8 p7.9 p7.10 p7.11 p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 p8.8 p8.9 p8.10 p8.11 p9.0 p9.1 p9.2 p9.3 p9.4 p9.5 p9.6 p9.7 p9.8 p9.9 p9. 10 p9.11 p14.0 p14.1 p14.2 p14.3 p14. 4 p14.5 p14.6 p14.7 p14.8 p14.9 p14.12 p14.13 p14.14 p14.15 p15. 2 p15.3 p15.4 p15.5 p15.6 p15.7 p15.8 p15.9 p15.12 p15.13 p15.14 p15.15 hib_i o_0 hib_i o_1 n.c . n.c . n.c . n.c . n.c . n.c . n.c . n.c . n.c . n.c . n.c . n.c . porst rtc _x tal2 rtc _x tal1 tck tms usb_d m usb_d p vag n d varef vbat vbus vd d a vddc vd d c vd d c vd d p vd d p vd d p vss vs s vs s vss vss vss vs s vss a vsso xtal1 xtal2 a a b b c c d d e e f f g g h h j j k k l l m m n n p p 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 xm c 4[78 ]00 ?\ (top ? view ) subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 21 v0.7, 2015-10 figure 7 xmc4[78]00 pg-lqfp-100 pin configuration (top view) 2 p0 . 0 1 p0 . 1 10 0 p 0 .2 99 p0.3 98 p0.4 97 p0.5 96 p0.6 89 p0.7 88 p0.8 4 p0 . 9 3 p0 . 1 0 95 p0.11 94 p0.12 79 p1.0 78 p1.1 77 p1.2 76 p1.3 75 p1.4 74 p1.5 83 p1.6 82 p1.7 81 p1.8 80 p1.9 73 p1.10 72 p1.11 71 p1.12 70 p1.13 69 p1.14 68 p1.15 52 p2.0 51 p2.1 50 p2.2 49 p2.3 48 p2.4 47 p2.5 54 p2.6 53 p2.7 46 p2.8 45 p2.9 44 p2.10 41 p2.14 40 p2.15 7 p3 . 0 6 p3 . 1 5 p3 . 2 93 p3.3 92 p3.4 91 p3.5 90 p3.6 85 p4.0 84 p4.1 58 p5.0 57 p5.1 56 p5.2 55 p5.7 31 p14.0 30 p14.1 29 p14.2 28 p14.3 27 p14.4 26 p14.5 25 p1 4 . 6 24 p1 4 . 7 37 p14.8 36 p14.9 23 p14.12 22 p14.13 21 p14.14 20 p14.15 19 p1 5 . 2 18 p1 5 . 3 39 p15.8 38 p15.9 14 hib_io _0 13 hib_io _1 65 porst 15 rtc_xtal2 16 rtc_xtal1 67 tck 66 tms 8 usb _dm 9 usb_dp 32 vagnd 33 va r ef 17 vbat 10 vbus 35 vd d a 12 vddc 42 vddc 64 vddc 86 vddc 11 vddp 43 vd d p 60 vddp 87 vddp 59 vss 34 vssa 63 vsso 61 xtal1 62 xtal2 xmc4[78]00 (top view) subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 22 v0.7, 2015-10 2.2.1 package pin summary the following general scheme is used to describe each pin: the table is sorted by the ?function? column, starting with the regular port pins (px.y), followed by the dedicated pins (i.e. porst ) and supply pins. the following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package. the ?pad type? indicates the employed pad type (a1, a1+, a2, special=special pad, in=input pad, an/dig_in=analog and digital input, power=power supply). details about the pad properties are defined in the electrical parameters. in the ?notes?, special information to the res pective pin/function is given, i.e. deviations from the default configuration after reset. per default the regular port pins are configured as direct input with no internal pull device active. table 9 package pin mapping description function package a package b ... pad type notes name n ax ... a2 table 10 package pin mapping function lfbga-196 lqfp-144 lqfp-100 pad type notes p0.0 e4 2 2 a1+ p0.1 e3 1 1 a1+ p0.2 c3 144 100 a2 p0.3 c4 143 99 a2 p0.4 d5 142 98 a2 p0.5 c5 141 97 a2 p0.6 c6 140 96 a2 p0.7 d7 128 89 a2 after a system reset, via hwsel this pin selects the db.tdi function. p0.8 c8 127 88 a2 after a system reset, via hwsel this pin selects the db.trst function, with a weak pull-down active. p0.9 f4 4 4 a2 p0.10 d4 3 3 a1+ subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 23 v0.7, 2015-10 p0.11 g5 139 95 a1+ p0.12 f5 138 94 a1+ p0.13 e5 137 - a1+ p0.14 g6 136 - a1+ p0.15 e6 135 - a1+ p1.0 f9 112 79 a1+ p1.1 g9 111 78 a1+ p1.2 e11 110 77 a2 p1.3 e12 109 76 a2 p1.4 e10 108 75 a1+ p1.5 f10 107 74 a1+ p1.6 d9 116 83 a2 p1.7 d10 115 82 a2 p1.8 c10 114 81 a2 p1.9 d11 113 80 a2 p1.10 f12 106 73 a1+ p1.11 f11 105 72 a1+ p1.12 g11 104 71 a2 p1.13 g12 103 70 a2 p1.14 g10 102 69 a2 p1.15 j12 94 68 a2 p2.0 l11 74 52 a2 p2.1 m12 73 51 a2 after a system reset, via hwsel this pin selects the db.tdo function. p2.2 m11 72 50 a2 p2.3 n11 71 49 a2 p2.4 n10 70 48 a2 p2.5 p10 69 47 a2 p2.6 l9 76 54 a1+ p2.7 m9 75 53 a1+ p2.8 n9 68 46 a2 p2.9 p9 67 45 a2 table 10 package pin mapping (cont?d) function lfbga-196 lqfp-144 lqfp-100 pad type notes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 24 v0.7, 2015-10 p2.10 n8 66 44 a2 p2.11 p8 65 - a2 p2.12 n7 64 - a2 p2.13 p7 63 - a2 p2.14 m7 60 41 a2 p2.15 l6 59 40 a2 p3.0 e1 7 7 a2 p3.1 d2 6 6 a2 p3.2 d3 5 5 a2 p3.3 h7 132 93 a1+ p3.4 g7 131 92 a1+ p3.5 d6 130 91 a2 p3.6 c7 129 90 a2 p3.7 g4 14 - a1+ p3.8 g3 13 - a1+ p3.9 h5 12 - a1+ p3.10 h6 11 - a1+ p3.11 f3 10 - a1+ p3.12 f2 9 - a2 p3.13 e2 8 - a2 p3.14 f6 134 - a1+ p3.15 f7 133 - a1+ p4.0 d8 124 85 a2 p4.1 c9 123 84 a2 p4.2 g8 122 - a1+ p4.3 h8 121 - a1+ p4.4 e7 120 - a1+ p4.5 f8 119 - a1+ p4.6 e8 118 - a1+ p4.7 e9 117 - a1+ p5.0 k9 84 58 a1+ p5.1 k8 83 57 a1+ p5.2 k7 82 56 a1+ table 10 package pin mapping (cont?d) function lfbga-196 lqfp-144 lqfp-100 pad type notes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 25 v0.7, 2015-10 p5.3 l10 81 - a2 p5.4 m10 80 - a2 p5.5 l8 79 - a2 p5.6 m8 78 - a2 p5.7 l7 77 55 a1+ p5.8 k6 58 - a2 p5.9 m6 57 - a2 p5.10 k5 56 - a1+ p5.11 l5 55 - a1+ p6.0 j10 101 - a2 p6.1 h9 100 - a2 p6.2 k10 99 - a2 p6.3 j9 98 - a1+ p6.4 h10 97 - a2 p6.5 h11 96 - a2 p6.6 h12 95 - a2 p7.0 l13 - - a2 p7.1 m13 - - a2 p7.2 n13 - - a2 p7.3 m14 - - a2 p7.4 n14 - - a1+ p7.5 l14 - - a1+ p7.6 k14 - - a1+ p7.7 j14 - - a1+ p7.8 h14 - - a2 p7.9 g13 - - a1+ p7.10 g14 - - a1+ p7.11 f14 - - a1+ p8.0 b7 - - a2 p8.1 a7 - - a2 p8.2 b3 - - a2 p8.3 b2 - - a2 p8.4 b6 - - a1+ table 10 package pin mapping (cont?d) function lfbga-196 lqfp-144 lqfp-100 pad type notes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 26 v0.7, 2015-10 p8.5 b5 - - a1+ p8.6 a2 - - a1+ p8.7 b4 - - a1+ p8.8 a3 - - a2 p8.9 a5 - - a1+ p8.10 a4 - - a1+ p8.11 a6 - - a1+ p9.0 f13 - - a2 p9.1 e14 - - a2 p9.2 d14 - - a1+ p9.3 d13 - - a2 p9.4 a12 - - a1+ p9.5 a11 - - a1+ p9.6 b11 - - a1+ p9.7 a9 - - a1+ p9.8 a8 - - a1+ p9.9 a10 - - a1+ p9.10 b8 - - a1+ p9.11 b9 - - a1+ p14.0 n3 42 31 an/dig_in p14.1 n2 41 30 an/dig_in p14.2 m3 40 29 an/dig_in p14.3 l4 39 28 an/dig_in p14.4 m1 38 27 an/dig_in p14.5 m2 37 26 an/dig_in p14.6 l3 36 25 an/dig_in p14.7 l2 35 24 an/dig_in p14.8 p5 52 37 an/dac/di g_in p14.9 n5 51 36 an/dac/di g_in p14.12 l1 34 23 an/dig_in p14.13 k4 33 22 an/dig_in table 10 package pin mapping (cont?d) function lfbga-196 lqfp-144 lqfp-100 pad type notes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 27 v0.7, 2015-10 p14.14 k3 32 21 an/dig_in p14.15 k2 31 20 an/dig_in p15.2 k1 30 19 an/dig_in p15.3 j2 29 18 an/dig_in p15.4 j4 28 - an/dig_in p15.5 j3 27 - an/dig_in p15.6 j5 26 - an/dig_in p15.7 j6 25 - an/dig_in p15.8 p6 54 39 an/dig_in p15.9 n6 53 38 an/dig_in p15.12 m5 50 - an/dig_in p15.13 p4 49 - an/dig_in p15.14 n4 44 - an/dig_in p15.15 m4 43 - an/dig_in usb_dp g1 16 9 special usb_dm f1 15 8 special hib_io_0 h4 21 14 a1 special at the first power-up and with every reset of the hibernate domain this pin is configured as open- drain output and drives "0". as output the medium driver mode is active. hib_io_1 h3 20 13 a1 special at the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. as output the medium driver mode is active. tck j8 93 67 a1 weak pull-down active. tms j7 92 66 a1+ weak pull-up active. as output the strong-soft driver mode is active. table 10 package pin mapping (cont?d) function lfbga-196 lqfp-144 lqfp-100 pad type notes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 28 v0.7, 2015-10 porst j11 91 65 special weak pull-up permanently active, strong pull-down controlled by evr. xtal1 k11 87 61 clock_in xtal2 k12 88 62 clock_o rtc_xtal1 h1 23 16 clock_in rtc_xtal2 h2 22 15 clock_o vbat j1 24 17 power when vddp is supplied vbat has to be supplied as well. vbus g2 17 10 special varef p3 46 33 an_ref vagnd p2 45 32 an_ref vdda n1 48 35 an_power vssa p1 47 34 an_power vddc - 19 12 power vddc - 61 42 power vddc - 90 64 power vddc - 125 86 power vddc c2 - - power vddc d12 - - power vddc p11 - - power vddp - 18 11 power vddp - 62 43 power vddp - 86 60 power vddp - 126 87 power vddp c11 - - power vddp d1 - - power vddp n12 - - power vss - 85 59 power vss a1 - - power vss a14 - - power vss b13 - - power vss c1 - - power table 10 package pin mapping (cont?d) function lfbga-196 lqfp-144 lqfp-100 pad type notes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 29 v0.7, 2015-10 vss c12 - - power vss p12 - - power vss p14 - - power vsso l12 89 63 power vss - exp. pad exp. pad power exposed die pad the exposed die pad is connected internally to vss. for proper operation, it is mandatory to connect the exposed pad directly to the common ground on the board. for thermal aspects, please refer to the data sheet. board layout examples are given in an application note. n.c. a13 - - - n.c. b1 - - - n.c. b10 - - - n.c. b12 - - - n.c. b14 - - - n.c. c13 - - - n.c. c14 - - - n.c. e13 - - - n.c. h13 - - - n.c. j13 - - - n.c. k13 - - - n.c. p13 - - - table 10 package pin mapping (cont?d) function lfbga-196 lqfp-144 lqfp-100 pad type notes subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family general device information preliminary data sheet 30 v0.7, 2015-10 2.2.2 port i/o functions the following general scheme is used to describe each port pin: figure 8 simplified port structure pn.y is the port pin name, defining the cont rol and data bits/registers associated with it. as gpio, the port is under software control. its input value is read via pn_in.y, pn_out defines the output value. up to four alternate output functions (a lt1/2/3/4) can be mapped to a single port pin, selected by pn_iocr.pc. the output value is directly driven by the respective module, with the pin characteristics controlled by th e port registers (wit hin the limits of the connected pad). the port pin input can be connected to mult iple peripherals. most peripherals have an input multiplexer to select between different possible input sources. the input path is also active while the pin is configured as output. th is allows to feedback an output to on-chip resources witho ut wasting an additional external pin. by pn_hwsel it is possible to select between different hardware ?masters? (hwo0/hwi0). the selected peripheral can take control of the pin(s). hardware control overrules settings in the respective port pin registers. table 11 port i/o function description function outputs inputs alt1 altn hwo0 hwi0 input input p0.0 moda.out modb.out modb.ina modc.ina pn.y moda.out moda.ina modc.inb xmc4000 pn.y v ddp gnd pn.y alt1 ... altn hwo0 hwo1 sw control logic input 0 input n ... pad hwi0 hwi1 modb.out modb moda moda.ina subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 31 v0.7, 2015-10 2.2.2.1 port i/o function table table 12 port i/o functions function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input p0.0 ecat0. phy_rst can. n0_txd ccu80. out21 ledts0. col2 u1c1. dx0d eth0. clk_rmiib eru0. 0b0 eth0. clkrxb p0.1 usb. drivevbus u1c1. dout0 ccu80. out11 ledts0. col3 eth0. crs_dvb eru0. 0a0 ecat0. p1_rx_clka eth0. rxdvb p0.2 ecat0. p1_txd2 u1c1. selo1 ccu80. out01 u1c0. dout3 ebu. ad0 u1c0. hwin3 ebu. d0 eth0. rxd0b eru0. 3b3 p0.3 ecat0. p1_txd3 ccu80. out20 u1c0. dout2 ebu. ad1 u1c0. hwin2 ebu. d1 eth0. rxd1b eru1. 3b0 p0.4 eth0. tx_en ccu80. out10 u1c0. dout1 ebu. ad2 u1c0. hwin1 ebu. d2 u1c0. dx0a eru0. 2b3 ecat0. p1_rxd3a p0.5 eth0. txd0 u1c0. dout0 ccu80. out00 u1c0. dout0 ebu. ad3 u1c0. hwin0 ebu. d3 u1c0. dx0b eru1. 3a0 eca t 0. p1_rxd2a p0.6 eth0. txd1 u1c0. selo0 ccu80. out30 ebu. adv u1c0. dx2a eru0. 3b2 ccu80. in2b ecat0. p1_rxd1a p0.7 wwdt. service_out u0c0. selo0 ecat0. led_err ebu. ad6 db. tdi ebu. d6 u0c0. dx2b dsd. din1a eru0. 2b1 ccu80. in0a ccu80. in1a ccu80. in2a ccu80. in3a p0.8 scu. extclk u0c0. sclkout ecat0. led_run ebu. ad7 db. trst ebu. d7 u0c0. dx1b dsd. din0a eru0. 2a1 can. n3_rxda ccu80. in1b p0.9 u1c1. selo0 ccu80. out12 ledts0. col0 eth0. mdo ebu. cs1 eth0. mdia u1c1. dx2a usb. id eru0. 1b0 ecat0. p1_rx_dva p0.10 eth0. mdc u1c1. sclkout ccu80. out02 ledts0. col1 u1c1. dx1a eru0. 1a0 ecat0. p1_tx_clka p0.11 ecat0. p1_link_act u1c0. sclkout ccu80. out31 sdmmc. rst ebu. breq eth0. rxerb u1c0. dx1a eru0. 3a2 ecat0. p1_rxd0a p0.12 u1c1. selo0 ccu40. out3 ecat0. mdo ebu. hlda ecat0. mdia ebu. hlda u1c1. dx2b eru0. 2b2 p0.13 u1c1. sclkout ccu40. out2 u1c1. dx1b eru0. 2a2 p0.14 u1c0. selo1 ccu40. out1 u1c1. dout3 u1c1. hwin3 ccu42. in3c p0.15 u1c0. selo2 ccu40. out0 u1c1. dout2 u1c1. hwin2 ccu42. in2c p1.0 dsd. cgpwmn u0c0. selo0 ccu40. out3 eru1. pdout3 u0c0. dx2a eru0. 3b0 ccu40. in3a ecat0. p0_tx_clka p1.1 dsd. cgpwmp u0c0. sclkout ccu40. out2 eru1. pdout2 sdmmc. sdwc u0c0. dx1a posif0. in2a eru0. 3a0 ccu40. in2a ecat0. p0_rx_clka p1.2 ecat0. p0_txd3 ccu40. out1 eru1. pdout1 u0c0. dout3 ebu. ad14 u0c0. hwin3 ebu. d14 posif0. in1a eru1. 2b0 ccu40. in1a p1.3 ecat0. p0_tx_ena u0c0. mclkout ccu40. out0 eru1. pdout0 u0c0. dout2 ebu. ad15 u0c0. hwin2 eb u . d15 posif0. in0a eru1. 2a0 ccu40. in0a p1.4 wwdt. service_out can. n0_txd ccu80. out33 ccu81. out20 u0c0. dout1 u0c0. hwin1 u0c0. dx0b can. n1_rxdd eru0. 2b0 ccu41. in0c ecat0. p0_rxd0a subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 32 v0.7, 2015-10 p1.5 can. n1_txd u0c0. dout0 ccu80. out23 ccu81. out10 u0c0. dout0 u0c0. hwin0 u0c0. dx0a can. n0_rxda eru0. 2a0 eru1. 0a0 ccu41. in1c dsd. din2b ecat0. p0_rxd1a p1.6 ecat0. p0_txd0 u0c0. sclkout sdmmc. data1_out ebu. ad10 sdmmc. data1_in ebu. d10 dsd. din2a p1.7 ecat0. p0_txd1 u0c0. dout0 dsd. mclk2 u1c1. selo2 sdmmc. data2_out ebu. ad11 sdmmc. data2_in ebu. d11 dsd. mclk2a dsd. mclk0c p1.8 ecat0. p0_txd2 u0c0. selo1 dsd. mclk1 u1c1. sclkout sdmmc. data4_out ebu. ad12 sdmmc. data4_in ebu. d12 can. n2_rxda dsd. mclk1a dsd. mclk0d dsd. mclk2d dsd. mclk3d p1.9 u0c0. sclkout can. n2_txd dsd. mclk0 u1c1. dout0 sdmmc. data5_out ebu. ad13 sdmmc. data5_in ebu. d13 ds d . mclk0a dsd. mclk1c dsd. mclk2c dsd. mclk3c ecat0. p0_rx_dva p1.10 eth0. mdc u0c0. sclkout ccu81. out21 ecat0. led_err sdmmc. sdcd ccu41. in2c ecat0. p0_rxd2a p1.11 ecat0. led_state_ru n u0c0. selo0 ccu81. out11 ecat0. led_run eth0. mdo eth0. mdic ccu41. in3c ecat0. p0_rxd3a p1.12 eth0. tx_en can. n1_txd ccu81. out01 ecat0. p0_link_act sdmmc. data6_out ebu. ad16 sdmmc. data6_in ebu. d16 p1.13 eth0. txd0 u0c1. selo3 ccu81. out20 ecat0. phy_clk25 sdmmc. data7_out ebu. ad17 sdmmc. data7_in ebu. d17 can. n1_rxdc p1.14 eth0. txd1 u0c1. selo2 ccu81. out10 ecat0. sync0 ebu. ad18 ebu. d18 u1c0. dx0e p1.15 scu. extclk dsd. mclk2 ccu81. out00 u1c0. dout0 ebu. ad19 ebu. d19 dsd. mclk2b eru1. 1a0 ecat0. p0_linkb p2.0 can. n0_txd ccu81. out21 dsd. cgpwmn ledts0. col1 eth0. mdo ebu. ad20 eth0. mdib ebu. d20 eru 0 . 0b3 ccu40. in1c p2.1 can. n5_txd ccu81. out11 dsd. cgpwmp ledts0. col0 db.tdo/ traceswo ebu. ad21 ebu. d21 eth0. clk_rmiia eru1. 0b0 ccu40. in0c eth0. clkrxa p2.2 vadc. emux00 ccu81. out01 ccu41. out3 ledts0. line0 ledts0. extended0 ebu. ad22 ledts0. tsin0a ebu. d22 eth0. rxd0a u0c1. dx0a eru0. 1b2 ccu41. in3a p2.3 vadc. emux01 u0c1. selo0 ccu41. out2 ledts0. line1 ledts0. extended1 ebu. ad23 ledts0. tsin1a ebu. d23 eth0. rxd1a u0c1. dx2a eru0. 1a2 posif1. in2a ccu41. in2a p2.4 vadc. emux02 u0c1. sclkout ccu41. out1 ledts0. line2 ledts0. extended2 ebu. ad24 ledts0. tsin2a ebu. d24 eth0. rxera u0c1. dx1a eru0. 0b2 posif1. in1a ccu41. in 1 a p2.5 eth0. tx_en u0c1. dout0 ccu41. out0 ledts0. line3 ledts0. extended3 ebu. ad25 ledts0. tsin3a ebu. d25 eth0. rxdva u0c1. dx0b eru0. 0a2 posif1. in0a ccu41. in0a eth0. crs_dva p2.6 u2c0. selo4 eru1. pdout3 ccu80. out13 ledts0. col3 u2c0. dout3 u2c0. hwin3 dsd. din1b can. n1_rxda eru0. 1b3 can. n5_rxdb ccu40. in3c ecat0. p0_rx_errb p2.7 eth0. mdc can. n1_txd ccu80. out03 ledts0. col2 dsd. din0b eru1. 1b0 ccu40. in2c p2.8 eth0. txd0 eru1. pdout1 ccu80. out32 ledts0. line4 ledts0. extended4 ebu. ad26 ledts0. tsin4a ebu. d26 dac. trigger5 ccu40. in0b ccu40. in1b ccu40. in2b ccu40. in3b p2.9 eth0. txd1 eru1. pdout2 ccu80. out22 ledts0. line5 ledts0. ex te nded5 ebu. ad27 ledts0. tsin5a ebu. d27 dac. trigger4 ccu41. in0b ccu41. in1b ccu41. in2b ccu41. in3b p2.10 vadc. emux10 eru1. pdout0 ecat0. phy_rst ecat0. sync1 db. etm_traceda ta3 ebu. ad28 ebu. d28 p2.11 eth0. txer ecat0. p1_txd0 ccu80. out22 db. etm_traceda ta2 ebu. ad29 ebu. d29 table 12 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 33 v0.7, 2015-10 p2.12 eth0. txd2 ecat0. p1_txd1 ccu81. out33 eth0. txd0 db. etm_traceda ta1 ebu. ad30 ebu. d30 ccu43. in3c p2.13 eth0. txd3 ecat0. p1_txd2 eth0. txd1 db. etm_traceda ta0 ebu. ad31 ebu. d31 ccu43. in2c p2.14 vadc. emux11 u1c0. dout0 ccu80. out21 can. n4_txd db. etm_traceclk ebu. bc0 u1c0. dx0d ccu43. in0b ccu43. in1b ccu43. in2b ccu43. in3b p2.15 vadc. emux12 ecat0. p1_txd3 ccu80. out11 ledts0. line6 ledts0. extended6 ebu. bc1 ledts0. tsin6a eth0. cola u1c0. dx0c can. n4_rxda ccu42. in0b ccu42. in1b ccu42. in2b ccu42. in3b p3.0 u2c1. selo0 u0c1. sclkout ccu42. out0 ecat0. p1_tx_ena ebu. rd u0c1. dx1b ccu80. in2c ccu81. in0c p3.1 u0c1. selo0 ecat0. p1_txd0 ebu. rd_wr u0c1. dx2b eru0. 0b1 ccu80. in1c p3.2 usb. drivevbus can. n0_txd ecat0. p1_txd1 ledts0. cola ebu. cs0 eru0. 0a1 ccu80. in0c p3.3 u1c1. selo1 ccu42. out3 ecat0. mclk sdmmc. led ebu. wait dsd. din3b ccu42. in3a ccu80. in3b p3.4 u2c1. mclkout u1c1. selo2 ccu42. out2 dsd. mclk3 sdmmc. bus_power ebu. hold u2c1. dx0b dsd. mclk3b ccu42. in2a ccu80. in0b ecat0. p1_linka p3.5 u2c1. dout0 u1c1. selo3 ccu42. out1 u0c1. dout0 sdmmc. cmd_out ebu. ad4 sdmmc. cmd_in ebu. d4 u2c1. dx0a eru0. 3b1 ccu42. in1a ecat0. p1_rx_erra p3.6 u2c1. sclkout u1c1. selo4 ccu42. out0 u0c1. sclkout sdmmc. clk_out ebu. ad5 sdmmc. clk_in ebu. d5 u2c1. dx1b eru0. 3a1 ccu42. in0a p3.7 ecat0. sync0 can. n2_txd ccu41. out3 ledts0. line0 u2c0. dx0c p3.8 u2c0. dout0 u0c1. selo3 ccu41. out2 ledts0. line1 can. n2_rxdb posif1. in2b p3.9 u2c0. sclkout can. n1_txd ccu41. out1 ledts0. line2 posif1. in1b p3.10 u2c0. selo0 can. n0_txd ccu41. out0 ledts0. line3 u0c1. dout3 u0c1. hwin3 posif1. in0b p3. 1 1 u2c1. dout0 u0c1. selo2 ccu42. out3 ledts0. line4 u0c1. dout2 u0c1. hwin2 can. n1_rxdb ccu81. in3c p3.12 ecat0. p1_link_act u0c1. selo1 ccu42. out2 ledts0. line5 u0c1. dout1 u0c1. hwin1 can. n0_rxdc u2c1. dx0d ccu81. in2c p3.13 u2c1. sclkout u0c1. dout0 ccu42. out1 ledts0. line6 u0c1. dout0 u0c1. hwin0 u0c1. dx0d ccu80. in3c ccu81. in1c p3.14 u1c0. selo3 u1c1. dout1 u1c1. hwin1 u1c1. dx0b ccu42. in1c p3.15 u1c1. dout0 u1c1. dout0 u1c1. hwin0 u1c1. dx0a ccu42. in0c p4.0 can. n3_txd ecat0. phy_clk25 dsd. mclk1 u1c0. sclkout sdmmc. data0_out ebu. ad8 sdmmc. data0_in ebu. d8 u1c1. dx1c dsd. mclk1b u0c1. dx0e u2c1. dx0c ecat0. p0_rx_erra p4.1 u2c1. selo0 u1c1. mc lko ut dsd. mclk0 u0c1. selo0 sdmmc. data3_out ebu. ad9 sdmmc. data3_in ebu. d9 u2c1. dx2b dsd. mclk0b u2c1. dx2a dsd. mclk1d ecat0. p0_linka p4.2 u2c1. selo1 u1c1. dout0 u2c1. sclkout ecat0. mdo ecat0. mdib u1c1. dx0c u2c1. dx1a ccu43. in1c table 12 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 34 v0.7, 2015-10 p4.3 u2c1. selo2 u0c0. selo5 ccu43. out3 ecat0. mclk ccu43. in3a p4.4 u0c0. selo4 ccu43. out2 u2c1. dout3 u2c1. hwin3 ccu43. in2a p4.5 u0c0. selo3 ccu43. out1 u2c1. dout2 u2c1. hwin2 ccu43. in1a p4.6 u0c0. selo2 ccu43. out0 u2c1. dout1 u2c1. hwin1 can. n2_rxdc u2c1. dx0e ccu43. in0a p4.7 u2c1. dout0 can. n2_txd u2c1. dout0 u2c1. hwin0 u0c0. dx0c ccu43. in0c p5.0 u2c0. dout0 dsd. cgpwmn ccu81. out33 eru1. pdout0 u2c0. dout0 u2c0. hwin0 u2c0. dx0b eth0. rxd0d u0c0. dx0d ecat0. p0_rxd0b ccu81. in0a ccu81. in1a ccu81. in2a ccu81. in3a p5.1 u0c0. dout0 dsd. cgpwmp ccu81. out32 eru1. pdout1 u2c0. dout1 u2c0. hwin1 u2c0. dx0a eth0. rxd1d ecat0. p0_rxd1b ccu 81 . in0b p5.2 u2c0. sclkout ecat0. p0_link_act ccu81. out23 eru1. pdout2 u2c0. dx1a eth0. crs_dvd ecat0. p0_rxd2b ccu81. in1b eth0. rxdvd p5.3 u2c0. selo0 ccu81. out22 eru1. pdout3 ebu. cke ebu. a20 u2c0. dx2a eth0. rxerd ccu81. in2b p5.4 u2c0. selo1 ccu81. out13 ebu. ras ebu. a21 eth0. crsd ccu81. in3b ecat0. p0_rx_clkb p5.5 u2c0. selo2 ccu81. out12 ebu. cas ebu. a22 eth0. cold ecat0. p0_tx_clkb p5.6 u2c0. selo3 ccu81. out03 ebu. bfclko ebu. a23 ebu. bfclki ecat0. p0_rx_dvb p5.7 ecat0. sync0 ccu81. out02 ledts0. cola u2c0. dout2 u2c0. hwin2 ecat0. p0_rxd3b p5.8 ecat0. p1_tx_ena u1c0. sclkout ccu80. out01 can. n4_txd ebu. sdclko ebu. cs2 eth0. rxd2a u1c0. dx1b p5.9 u1c0. selo0 ccu80. out20 eth0. tx_en ebu. bfclko ebu. cs3 eth0. rxd3a u1c0. dx2b ecat0. p1_tx_clkb p5.10 u1c0. mclkout ccu80. out10 ledts0. line7 ledts0. extended7 ledts0. tsin7a eth0. clk_txa can. n5_rxda p5.11 u1c0. selo1 ccu80. out00 can. n5_txd eth0. crsa p6.0 eth0. txd2 u0c1. selo1 ccu81. out31 ecat0. phy_clk25 db. etm_traceclk ebu. a16 p6.1 eth0. txd3 u0c1. selo0 ccu81. out30 ecat0. p0_tx_ena db. etm_traceda ta3 ebu. a17 u0c1. dx2c p6.2 eth0. txer u0c1. sclkout ccu43. out3 ecat0. p0_txd0 db. etm_traceda ta2 ebu. a18 u0c1. dx1c p6.3 ccu43. out2 ecat0. p0_link_act u0c1. dx0c eth0. rxd3b p6.4 u0c1. dout0 ccu43. out1 ecat0. p0_txd1 ebu. sdclko ebu. a19 ebu. sdclki eth0. rxd2b p6.5 can. n3_txd u0c1. mclkout ccu43. out0 ecat0. p0_txd2 db. etm_traceda ta1 eb u . bc2 dsd. din3a eth0. clk_rmiid u2c0. dx0d eth0. clkrxd table 12 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 35 v0.7, 2015-10 p6.6 u2c0. dout0 dsd. mclk3 ecat0. p0_txd3 db. etm_traceda ta0 ebu. bc3 dsd. mclk3a eth0. clk_txb can. n3_rxdb p7.0 can. n3_txd ecat0. p0_txd0 ebu. a19 p7.1 ecat0. p0_txd1 ebu. a20 can. n3_rxdc p7.2 can. n4_txd ecat0. p0_txd2 ebu. a21 p7.3 ecat0. p0_txd3 ebu. a22 can. n4_rxdc p7.4 ccu42. out0 ecat0. p0_rxd0c p7.5 ccu42. out1 ecat0. p0_rxd1c p7.6 ccu42. out2 ecat0. p0_rxd2c p7.7 ccu42. out3 ecat0. p0_rxd3c p7.8 can. n5_txd ecat0. p0_tx_ena db. etm_traceclk p7.9 ccu80. out22 ecat0. p0_rx_errc p7.10 ccu80. out32 ecat0. p0_rx_clkc p7.11 ccu80. out33 ecat0. p0_rx_dvc p8.0 ecat0. p1_txd0 db. etm_traceda ta0 can. n5_rxdc p8.1 ecat0. p1_txd1 db. etm_traceda ta1 u0c0. dx2c p8.2 ecat0. p1_txd2 db. etm_traceda ta2 p8.3 ecat0. p1_txd3 db. etm_traceda ta3 u0c0. dx1c p8.4 u0c0. selo1 ecat0. p1_rxd0c p8.5 u0c0. sclkout ecat0. p1_rxd1c p8.6 u0c0. selo0 ecat0. p1_rxd2c p8.7 u0c0. dout0 ecat0. p1_rxd3c p8. 8 ec at0. p1_tx_ena u0c0. dx0e table 12 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 36 v0.7, 2015-10 p8.9 ccu81. out33 ecat0. p1_rx_errc p8.10 ccu81. out21 ecat0. p1_rx_clkc p8.11 ccu81. out11 ecat0. p1_rx_dvc p9.0 u2c0. selo0 ecat0. sync0 ecat0. latch0b u2c0. dx2c ecat0. p1_tx_clkc p9.1 u2c0. sclkout ecat0. sync1 ecat0. latch1b u2c0. dx1c ecat0. p0_tx_clkc p9.2 u2c0. selo1 ecat0. phy_rst eth0. colc p9.3 u2c0. dout0 ecat0. phy_clk25 eth0. crsc p9.4 ecat0. led_state_ru n ecat0. led_run u2c0. dx0e p9.5 u2c0. selo2 ecat0. led_err eth0. rxd2c p9.6 u2c0. selo3 ecat0. mclk eth0. rxd3c p9.7 u2c0. selo4 ecat0. mdo ecat0. mdic eth0. rxerc p9.8 ecat0. p0_link_act u2c1. dx2c p9.9 ecat0. p1_link_act u2c1. dx1c p9.10 u2c1. dout0 ecat0. p0_linkc p9.11 u2c1. selo3 ecat0. p1_linkc p14.0 vadc. g0ch0 p14.1 vadc. g0ch1 p14.2 vadc. g0ch2 vadc. g1ch2 p14.3 vadc. g0ch3 vadc. g1 ch 3 can. n0_rxdb p14.4 vadc. g0ch4 vadc. g2ch0 can. n4_rxdb ecat0. latch1a p14.5 vadc. g0ch5 vadc. g2ch1 posif0. in2b ecat0. latch0a p14.6 vadc. g0ch6 posif0. in1b g0orc6 ecat0. p1_rx_clkb p14.7 vadc. g0ch7 posif0. in0b g0orc7 ecat0. p1_rxd0b table 12 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 37 v0.7, 2015-10 p14.8 dac. out_0 vadc. g1ch0 vadc. g3ch2 eth0. rxd0c p14.9 dac. out_1 vadc. g1ch1 vadc. g3ch3 eth0. rxd1c p14.12 vadc. g1ch4 ecat0. p1_rxd1b p14.13 vadc. g1ch5 ecat0. p1_rxd2b p14.14 vadc. g1ch6 g1orc6 ecat0. p1_rxd3b p14.15 vadc. g1ch7 g1orc7 ecat0. p1_rx_dvb p15.2 vadc. g2ch2 ecat0. p1_rx_errb p15.3 vadc. g2ch3 ecat0. p1_linkb p15.4 vadc. g2ch4 p15.5 vadc. g2ch5 p15.6 vadc. g2ch6 p15.7 vadc. g2ch7 p15.8 vadc. g3ch0 eth0. clk_rmiic eth0. clkrxc p15.9 vadc. g3ch1 eth0. crs_dvc eth0. rxdvc p15.12 vadc. g3ch4 p15.13 vadc. g3ch5 p15.14 vadc. g3ch6 p15.15 vadc. g3ch7 usb_dp usb_dm hib_io_0 hibout wwdt. service_out wakeupa hib_io_1 hibout wwdt. service_out wakeupb tck db.tck/ swclk tms db.tms/ swdio porst table 12 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 38 v0.7, 2015-10 xtal1 u0c0. dx0f u0c1. dx0f u1c0. dx0f u1c1. dx0f u2c0. dx0f u2c1. dx0f xtal2 rtc_xtal1 eru0. 1b1 rtc_xtal2 table 12 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 hwo0 hwo1 hwi0 hwi1 input input input input input input input input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 39 v0.7, 2015-10 2.3 power connection scheme figure 9 . shows a reference power connection scheme for the xmc4[78]00. figure 9 power connection scheme every power supply pin needs to be connected. different pins of the same supply need also to be externally connected. as example, all v ddp pins must be connected externally to one v ddp net. in this reference scheme one 100 nf capacitor is connected at each supply pin against v ss . an additional 10 f capacitor is connected to the v ddp nets and an additional 10 uf capacitor to the v ddc nets. v bat m x v ddc n x v ddp v ss v dda v aref v agnd hibernate domain rtc hibernate control retention memory 32 khz clock core domain cpu dig. peripherals analog domain adc dac gpios out-of-range comparator pad domain level shift. flash rams 100 nf x m 10 f x 1 100 nf reference 100 nf 3.3v xmc4000 evr v ssa exp. die pad v ss gnd gnd gnd gnd agnd 100 nf x n 10 f x 1 3.3v 2.1...3.6 v subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family preliminary data sheet 40 v0.7, 2015-10 the xmc4[78]00 has a comm on ground concept, all v ss , v ssa and v sso pins share the same ground potential. in packages with an ex posed die pad it must be connected to the common ground as well. v agnd is the low potential to the analog reference v aref . depending on the application it can share the common ground or have a diff erent potential. in devices with shared v dda / v aref and v ssa / v agnd pins the reference is tied to the supply. some analog channels can optionally serve as ?alternate reference?; furthe r details on this operating mode are described in the reference manual. when v ddp is supplied, v bat must be supplied as well. if no other supply source (e.g. battery) is connected to v bat , the v bat pin can also be connected directly to v ddp . subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 41 v0.7, 2015-10 3 electrical parameters attention: all parameters in this chapter are preliminary target values and may change based on characterization results. 3.1 general parameters 3.1.1 parameter interpretation the parameters listed in this section par tly represent the characteristics of the xmc4[78]00 and partly its requirements on the system. to aid interpreting the parameters easily when evaluating them for a design, they are marked with a two-letter abbreviation in column ?symbol?: ? cc such parameters indicate c ontroller c haracteristics, which ar e a distinctive feature of the xmc4[78]00 and must be regarded for system design. ? sr such parameters indicate s ystem r equirements, which must be provided by the application system in which the xmc4[78]00 is designed in. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 42 v0.7, 2015-10 3.1.2 absolute maximum ratings stresses above the values listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a st ress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect device reliability. figure 10 explains the input voltage ranges of v in and v ain and its dependency to the supply level of v ddp .the input voltage must not exceed 4.3 v, and it must not be more than 1.0 v above v ddp . for the range up to v ddp + 1.0 v also see the definition of the overload conditions in section 3.1.3 . table 13 absolute maximum rating parameters parameter symbol values unit note / test con dition min. typ. max. storage temperature t st sr -65 ? 150 t j sr -40 ? v ss v ddp sr ? ? 4.3 v ? voltage on any class a and dedicated input pin with respect to v ss v in sr -1.0 ? v ddp + 1.0 or max. 4.3 v whichever is lower voltage on any analog input pin with respect to v agnd v ain v aref sr -1.0 ? v ddp + 1.0 or max. 4.3 v whichever is lower input current on any pin during overload condition i in sr -10 ? +10 ma absolute maximum sum of all input circuit currents for one port group during overload condition 1) 1) the port groups are defined in table 17 . i in sr -25 ? +25 ma absolute maximum sum of all input circuit currents during overload condition i in sr -100 ? +100 ma subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 43 v0.7, 2015-10 figure 10 absolute maximum input voltage ranges 3.1.3 pin reliability in overload when receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own io power supplies specification. table 14 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: ? full operation life-time is not exceeded ? operating conditions are met for ? pad supply levels ( v ddp or v dda ) ? temperature if a pin current is outside of the operating conditions but within the overload conditions, then the parameters of this pin as stated in t he operating conditions can no longer be guaranteed. operat ion is still possible in mo st cases but with relaxed parameters. note: an overload condition on one or more pins does not require a reset. note: a series resistor at the pin to limit the current to the maxi mum permitted overload current is sufficient to handle failur e situations like short to battery. v 4.3 v ss -1.0 a a b abs. max. input voltage v in with v ddp > 3.3 v abs. max. input voltage v in with v ddp 3.3 v v v ddp + 1.0 v ss -1.0 v ddp b subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 44 v0.7, 2015-10 figure 11 shows the path of the input currents during overload via the esd protection structures. the diodes against v ddp and ground are a simplified representation of these esd protection structures. figure 11 input overload current via esd structures table 15 and table 16 list input voltages that can be reached under overload conditions. note that the absolute maximum input voltages as defined in the absolute maximum ratings must not be exceeded during overload. table 14 overload parameters parameter symbol values unit note / test condition min. typ. max. input current on any port pin during overload condition i ov sr -5 ? 5 ma absolute sum of all input circuit currents for one port group during overload condition 1) 1) the port groups are defined in table 17 . i ovg sr ? ? 20 ma | i ovx |, for all i ovx < | i ovx |, for all i ovx > i ovs sr ? ? 80 ma i ovg pn.y i ovx gnd esd pad gnd v ddp v ddp subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 45 v0.7, 2015-10 table 15 pn-junction characteris itics for positive overload pad type i ov =5ma, t j =-40c i ov =5ma, t j =150c a1 / a1+ v in = v ddp +1.0v v in = v ddp +0.75v a2 v in = v ddp +0.7v v in = v ddp +0.6v an/dig_in v in = v ddp +1.0v v in = v ddp +0.75v table 16 pn-junction characterisitics for negative overload pad type i ov =5ma, t j =-40c i ov =5ma, t j =150c a1 / a1+ v in = v ss -1.0v v in = v ss -0.75v a2 v in = v ss -0.7v v in = v ss -0.6v an/dig_in v in = v ddp -1.0v v in = v ddp -0.75v table 17 port groups for overload and short-circuit current sum parameters group pins 1 p0.[15:0], p3.[15:0], p8.[11:0] 2 p14.[15:0], p15.[15:0] 3 p2.[15:0], p5.[11:0], p7[11:0] 4 p1.[15:0], p4.[7:0], p6.[6:0], p9.[11:0] subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 46 v0.7, 2015-10 3.1.4 pad driver and pad classes summary this section gives an overview on the different pad driver classes and their basic characteristics. figure 12 output slopes with different pad driver modes figure 12 is a qualitative display of the resulting output slope performance with different output driver modes. the detailed input and output characteristics are listed in section 3.2.1 . table 18 pad driver and pad classes overview class power supply type sub-class speed grade load termination a 3.3 v lvttl i/o a1 (e.g. gpio) 6 mhz 100 pf no a1+ (e.g. serial i/os) 25 mhz 50 pf series termination recommended a2 (e.g. ext. bus) 80 mhz 15 pf series termination recommended v v ddp v ss v oh v ol t a b c d e f a b c d e f o u t p u t h i g h v o l t a g e o u t p u t l o w v o l t a g e weak drive strength medium drive strength strong ? slow drive strength strong ? soft drive strength strong ? medium drive strength strong ? sharp drive strength a b c e f class a2 pads c d e f class a1+ pads e f class a1 pads subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 47 v0.7, 2015-10 3.1.5 operating conditions the following operating conditions must not be exceeded in order to ensure correct operation and reliability of t he xmc4[78]00. all par ameters specified in the following sections refer to these operatin g conditions, unless noted otherwise. table 19 operating conditions parameters parameter symbol values unit note / test condition min. typ. max. ambient temperature t a sr -40 ? ? v ddp sr 3.13 1) 1) see also the supply monitoring thresholds, section 3.3.2 . 3.3 3.63 2) 2) voltage overshoot to 4.0 v is permissible at power-up and porst low, provided the pulse duration is less than 100 v ddc cc ? ? v ss sr 0 ?? v dda sr 3.0 3.3 3.6 2) v analog ground voltage for v dda v ssa sr -0.1 0 0.1 v battery supply voltage for hibernate domain v bat sr 1.95 ? v ddp is supplied v bat has to be supplied as well. system frequency f sys sr ?? i sc sr -5 ? table 17 . i sc_pg sr ?? i sc_d sr ?? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 48 v0.7, 2015-10 3.2 dc parameters 3.2.1 input/output pins the digital input stage of the shared analog/dig ital input pins is identical to the input stage of the standard digital input/output pins. the pull-up on the porst pin is identical to the pull-up on the standard digital input/output pins. note: these parameters are not subject to production test, but verified by design and/or characterization. table 20 standard pad parameters parameter symbol values unit note / test condition min. max. pin capacitance (digital inputs/outputs) c io cc ? i pdl | sr 150 ? v in v ddp 1) current required to override the pull device with the opposite logic level (?force current?). with active pull device, at load currents between force and keep current the input state is undefined. ? v in v ddp 2) load current at which the pull device still ma intains the valid logic level (?keep current?). with active pull device, at load currents between force and keep current the input state is undefined. pull-up current | i puh | sr ? v in v ddp 100 ? v in v ddp input hysteresis for pads of all a classes 3) 3) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it can not be guaranteed that it suppresses switching due to external system noise. hysa cc 0.1 v ddp ? t sf1 cc ? t sf2 cc 100 ? i ppd | cc 13 ? v in = subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 49 v0.7, 2015-10 figure 13 pull device input characteristics figure 13 visualizes the input characteristics with an active internal pull device: ? in the cases ?a? the internal pull device is overridden by a strong external driver; ? in the cases ?b? the internal pull device defines the input logical state against a weak external load. xmc4000 in i pdl a i pdl 150 b i pdl 10 v ddp gnd v v ddp v ss 0.6 x v ddp a 0.36 x v ddp b valid high valid low invalid digital input xmc4000 in i puh a i puh 100 b i puh 10 v v ddp v ss 0.6 x v ddp b 0.36 x v ddp a valid high valid low invalid digital input pull-down active pull-up active subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 50 v0.7, 2015-10 table 21 standard pads class_a1 parameter symbol values unit note / test condition min. max. input leakage current i oza1 cc -500 500 na 0 v v in v ddp input high voltage v iha1 sr 0.6 v ddp v ddp + 0.3 v max. 3.6 v input low voltage v ila1 sr -0.3 0.36 v ddp v output high voltage, pod 1) = weak v oha1 cc v ddp - 0.4 ? i oh ? i oh v ddp - 0.4 ? i oh ? i oh v ola1 cc ? i ol ? i ol t fa1 cc ? c l =20pf; pod 1) = weak 1) pod = pin out driver ? c l =50pf; pod 1) = medium rise time t ra1 cc ? c l =20pf; pod 1) = weak ? c l =50pf; pod 1) = medium table 22 standard pads class_a1+ parameter symbol values unit note / test condition min. max. input leakage current i oza1+ cc -1 1 v in v ddp input high voltage v iha1+ sr 0.6 v ddp v ddp + 0.3 v max. 3.6 v input low voltage v ila1+ sr -0.3 0.36 v ddp v subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 51 v0.7, 2015-10 output high voltage, pod 1) = weak v oha1+ cc v ddp - 0.4 ? i oh ? i oh v ddp - 0.4 ? i oh ? i oh v ddp - 0.4 ? i oh ? i oh v ola1+ cc ? i ol ? i ol ? i ol t fa1+ cc ? c l =20pf; pod 1) = weak ? c l =50pf; pod 1) = medium ? c l =50pf; pod 1) = strong; edge = slow ? c l =50pf; pod 1) = strong; edge = soft; rise time t ra1+ cc ? c l =20pf; pod 1) = weak ? c l =50pf; pod 1) = medium ? c l =50pf; pod 1) = strong; edge = slow ? c l =50pf; pod 1) = strong; edge = soft 1) pod = pin out driver table 22 standard pads class_a1+ parameter symbol values unit note / test condition min. max. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 52 v0.7, 2015-10 table 23 standard pads class_a2 parameter symbol values unit note / test condition min. max. input leakage current i oza2 cc -6 6 v in < 0.5* v ddp -1v; 0.5* v ddp +1v < v in v ddp -3 3 v ddp -1v < v in <0.5* v ddp +1v input high voltage v iha2 sr 0.6 v ddp v ddp + 0.3 v max. 3.6 v input low voltage v ila2 sr -0.3 0.36 v ddp v output high voltage, pod = weak v oha2 cc v ddp - 0.4 ? i oh ? i oh v ddp - 0.4 ? i oh ? i oh v ddp - 0.4 ? i oh ? i oh v ola2 cc ? i ol ? i ol ? i ol subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 53 v0.7, 2015-10 fall time t fa2 cc ? c l =20pf; pod = weak ? c l =50pf; pod = medium ? c l =50pf; pod = strong; edge = sharp ? c l =50pf; pod = strong; edge = medium ? c l =50pf; pod = strong; edge = soft rise time t ra2 cc ? c l =20pf; pod = weak ? c l =50pf; pod = medium ? c l =50pf; pod = strong; edge = sharp ? c l =50pf; pod = strong; edge = medium ? c l =50pf; pod = strong; edge = soft table 23 standard pads class_a2 parameter symbol values unit note / test condition min. max. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 54 v0.7, 2015-10 3.2.2 analog to digital converters (vadc) note: these parameters are not subject to production test, but verified by design and/or characterization. table 24 vadc parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. analog reference voltage 5) v aref sr v agnd + 1 ? v dda + v agnd sr v ssm - 0.05 ? v aref - 1 v analog reference voltage range 2)5) v aref - v agnd sr 1 ? v dda + v ain sr v agnd ? v dda v input leakage at analog inputs 3) i oz1 cc -100 ? v dda < v ain < v dda -500 ? v ain v dda -100 ? v dda v ain v dda input leakage current at varef i oz2 cc -1 ? v aref v dda input leakage current at vagnd i oz3 cc -1 ? v agnd v dda internal adc clock f adci cc 2 ? v dda = 3.3 v switched capacitance at the analog voltage inputs 4) c ainsw cc ? c aintot cc ? c arefsw cc ? c areftot cc ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 55 v0.7, 2015-10 total unadjusted error tue cc -4 ? v dda = 3.3 v; v aref = v dda 7) differential non-linearity error 8) ea dnl cc -3 ? ea gain cc -4 ? ea inl cc -3 ? ea off cc -4 ? v dda power supply current per active converter i ddaa cc ? v ddp =3.6v, t j = 150 o c charge consumption on v aref per conversion 5) q conv cc ? ? v aref v dda 9) on resistance of the analog input path r ain cc ? r ain7t cc 180 550 900 ohm resistance of the reference voltage input path r aref cc ? v dda , then the adc converter errors increase. if the reference voltage is reduced by the factor k (k<1), tue, dnl, inl, ga in, and offset errors increase also by the factor 1/k. 3) the leakage current definition is a continuous function , as shown in figure adcx analog inputs leakage. the numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function (see figure 16 ). 4) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before the sampling moment. because of the parasitic elements, the voltage measured at ainx can deviate from v aref /2. 5) applies to ainx, when used as alternate reference input. 6) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead, smaller capacitances are successively switched to the reference voltage. 7) for 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16. never less than 1 lsb. 8) the sum of dnl/inl/gain/off errors does not exceed the related total unadjusted error tue. 9) the resulting current for a conversion can be calculated with i aref = q conv / t c . the fastest 12-bit post-calibrated conversion of t c = 459 ns results in a typical average current of i aref = 65.4 a. table 24 vadc parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 56 v0.7, 2015-10 figure 14 vadc reference voltage range the power-up calibration of the vadc requires a maximum number of 4 352 f adci cycles. figure 15 vadc input circuits minimum varef - vagnd is 1 v v v dda + 0.05 v agnd + 1 v agnd valid v aref v dda e.g. v aref = 4/5 of v dda conversion error increases by 5/4 precise conversion range (12 bit) t v aref v ssa reference voltage input circuitry analog input circuitry analog_inprefdiag r ext = v ain c ext r ain, on c aintot - c ainsw c ainsw anx v aref r aref, on c areftot - c arefsw c arefsw v agndx v arefx r ain7t v agndx subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 57 v0.7, 2015-10 figure 16 vadc analog input leakage current conversion time ? stc defines additional clock cycles to extend the sample time ? pc adds two cycles if post-calibration is enabled ? dm adds one cycle for an extended conversion time of the msb conversion time examples system assumptions: f adc = 144 mhz i.e. t adc = 6.9 ns, diva = 3, f adci = 36 mhz i.e. t adci = 27.8 ns according to the given formulas the following minimum conversion times can be achieved (stc = 0, dm = 0): 12-bit post-calibrated conversion (pc = 2): t cn12c = (2 + 12 + 2) t adci + 2 t adc = 16 t cn12 = (2 + 12) t adci + 2 t adc = 14 t cn10 = (2 + 10) t adci + 2 t adc = 12 t cn8 = (2 + 8) t adci + 2 t adc = 10 table 25 conversion time (operating conditions apply) parameter symbol values unit note conversion time t c cc 2 t adc + (2+n+stc+pc+dm) t adci t adc =1/ f periph t adci =1/ f adci adc-leakage.vsd v in [% v dda ] 200 na 500 na 3 % 100 % 97 % i oz1 100 na -500 na -100 na single adc input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 58 v0.7, 2015-10 3.2.3 digital to analog converters (dac) note: these parameters are not subject to production test, but verified by design and/or characterization. table 26 dac parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. rms supply current i dd cc ? res cc ? ? f urate_a cc ? f urate_f cc ? t settle cc ? sr cc 2 5 ? v out_min cc ? ? v out_max cc ? ? inl cc -4 2.5 4 lsb r l dnl cc -2 1 2 lsb r l subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 59 v0.7, 2015-10 conversion calculation unsigned: dacxdata = 4095 v out - v out_min ) / ( v out_max - v out_min ) signed: dacxdata = 4095 v out - v out_min ) / ( v out_max - v out_min ) - 2048 offset error ed off cc 20 mv gain error ed g_in cc -6.5 -1.5 3 % startup time t startup cc ? f c1 cc 2.5 5 ? i out_source cc ? ? i out_sink cc ? ? r out cc ? ? r l sr 5 ?? c l sr ?? snr cc ? ? thd cc ? ? psrr cc ? ? v dda verified by design table 26 dac parameters (operating conditions apply) (cont?d) parameter symbol values unit note / test condition min. typ. max. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 60 v0.7, 2015-10 figure 17 dac conversion examples dac output v out_min v out_max 64 lsbs +/- 4lsb f urate_f (max) 64 lsbs +/- 1lsb f urate_a (max) dac output v out_min v out_max 20 lsbs t settle 20 lsbs t settle subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 61 v0.7, 2015-10 3.2.4 out-of-range comparator (orc) the out-of-range comparator (orc) triggers on analog input voltages ( v ain ) above the analog reference 1) ( v aref ) on selected input pins (g xorcy) and generates a service request trigger (gxorcouty). note: these parameters are not subject to production test, but verified by design and/or characterization. the parameters in table 27 apply for the maximum reference voltage v aref = v dda +50mv. 1) always the standard vadc reference, alternate references do not apply to the orc. table 27 orc parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. dc switching level v odc cc 100 125 210 mv v ain v aref + v odc hysteresis v ohys cc 50 ? v odc mv detection delay of a persistent overvoltage t odd cc 50 ? v ain v aref + 210 mv 45 ? v ain v aref + 400 mv always detected overvoltage pulse t opdd cc 440 ?? v ain v aref + 210 mv 90 ?? v ain v aref + 400 mv never detected overvoltage pulse t opdn cc ?? v ain v aref + 210 mv ?? v ain v aref + 400 mv release delay t ord cc 65 ? v ain v aref enable delay t oed cc ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 62 v0.7, 2015-10 figure 18 gxorcouty trigger generation figure 19 orc detection ranges v ss v aref t ord v odc v ohys t odd gxorcouty gxorcy v ain (v) v aref + 400 mv t v aref + 200 mv overvoltage may be detected (level uncertain) never detected overvoltage pulse (too short) t < t opdn t opdn < t < t opdd overvoltage may be detected t > t opdd always detected overvoltage pulse t < t opdn never detected overvoltage pulse (too short) t opdn < t < t opdd t > t opdd always detected overvoltage pulse v aref + 100 mv overvoltage may be detected t > t opdn never detected overvoltage pulse (too low) v aref subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 63 v0.7, 2015-10 3.2.5 die temperature sensor the die temperature sensor (dts) measures the junction temperature t j . note: these parameters are not subject to production test, but verified by design and/or characterization. the following formula calculates the temperature measured by the dts in [ o c] from the result bit field of the dtsstat register. temperature t dts = (result - 605) / 2.05 [c] this formula and the values defined in table 28 apply with the following calibration values: ? dtscon.bgtrim = 8 h ? dtscon.reftrim = 4 h table 28 die temperature sensor parameters parameter symbol values unit note / test condition min. typ. max. temperature sensor range t sr sr -40 ? t le cc ? ? t j t oe cc ? ? t oe = t j - t dts v ddp v ddp_max = 3.63 v the typical offset error increases by an additional t oe =1c. measurement time t m cc ?? t tsst sr ?? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 64 v0.7, 2015-10 3.2.6 usb otg interface dc characteristics the universal serial bus (usb) interface is compliant to the usb rev. 2.0 specification and the otg specification rev. 1.3. high-speed mode is not supported. note: these parameters are not subject to production test, but verified by design and/or characterization. table 29 usb otg vbus and id parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. vbus input voltage range v in cc 0.0 ? v b1 cc 4.4 ?? v b2 cc 0.8 ? v b3 cc 0.8 ? v b4 cc 0.2 ? r vbus_in cc 40 ? r vbus_pu cc 281 ?? r vbus_pd cc 656 ?? r uid_pu cc 14 ? i vbus_in cc ?? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 65 v0.7, 2015-10 table 30 usb otg data line (usb_dp, usb_dm) parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. input low voltage v il sr ?? v ih sr 2.0 ?? v ihz sr 2.7 ? v dis cc 0.2 ?? v cm cc 0.8 ? v ol cc 0.0 ? v oh cc 2.8 ? r pui cc 900 ? r pua cc 1 425 ? r pd cc 14.25 ? z inp cc 300 ?? z drv cc 28 ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 66 v0.7, 2015-10 3.2.7 oscillator pins note: it is strongly recomm ended to measure the oscill ation allowance (negative resistance) in the final target system (layout) to determine th e optimal parameters for the oscillator operation. please refer to the limits specified by the crystal or ceramic resonator supplier. note: these parameters are not subject to production test, but verified by design and/or characterization. the oscillator pins can be operated with an external crystal (see figure 20 ) or in direct input mode (see figure 21 ). figure 20 oscillator in crystal mode xtal1 xtal2 f os c damping resistor may be needed for some crystals v ppx v ppx_min v ppx v ppx_max t v v ppx_min t os cs gnd subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 67 v0.7, 2015-10 figure 21 oscillator in direct input mode v v ihbx_max v ss t i n p u t h i g h v o l t a g e i n p u t l o w v o l t a g e i n p u t h i g h v o l t a g e xtal1 xtal2 not connected external clock source direct input mode v ihbx_min v ilbx_max v ilbx_min subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 68 v0.7, 2015-10 table 31 osc_xtal parameters parameter symbol values unit note / test condition min. typ. max. input frequency f osc sr 4 ? ? t oscs is defined from the moment the oscillator is enabled wih scu_oschpctrl.mode until the oscillations reach an amplitude at xtal1 of 0.4 * v ddp . 2) the external oscillator circuitry must be optimize d by the customer and check ed for negative resistance and amplitude as recommended and specified by crystal suppliers. t oscs cc ?? v ix sr -0.5 ? v ddp + 0.5 v input amplitude (peak- to-peak) at xtal1 2)3) 3) if the shaper unit is enabled and not bypassed. v ppx sr 0.4 v ddp ? v ddp + 1.0 v input high voltage at xtal1 4) 4) if the shaper unit is bypassed, dedicated dc-thresholds have to be met. v ihbx sr 1.0 ? v ddp + 0.5 v input low voltage at xtal1 4) v ilbx sr -0.5 ? i ilx1 cc -100 ? v ix v ddp subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 69 v0.7, 2015-10 table 32 rtc_xtal parameters parameter symbol values unit note / test condition min. typ. max. input frequency f osc sr ? ? t oscs is defined from the moment the oscillator is en abled by the user with scu_osculctrl.mode until the oscillations reach an amplitude at rtc_xtal1 of 400 mv. 2) the external oscillator circuitry must be optimize d by the customer and check ed for negative resistance and amplitude as recommended and specified by crystal suppliers. 3) for a reliable start of the oscillation in crystal mode it is required that v bat v bat voltage range. t oscs cc ?? v ix sr -0.3 ? v bat + 0.3 v input amplitude (peak- to-peak) at rtc_xtal1 2)4) 4) if the shaper unit is enabled and not bypassed. v ppx sr 0.4 ?? v ihbx sr 0.6 v bat ? v bat + 0.3 v input low voltage at rtc_xtal1 5) v ilbx sr -0.3 ? v bat v input hysteresis for rtc_xtal1 5)6) 6) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it can not be guaranteed that it suppresses switching due to external system noise. v hysx cc 0.1 v bat ? v bat <3.6v 0.03 v bat ? v bat <3.0v input leakage current at rtc_xtal1 i ilx1 cc -100 ? v ix v bat subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 70 v0.7, 2015-10 3.2.8 power supply current the total power supply current defined belo w consists of a leakage and a switching component. application relevant values are typically lowe r than those given in the following tables, and depend on the customer's system operat ing conditions (e.g. thermal connection or used application configurations). note: these parameters are not subject to production test, but verified by design and/or characterization. if not stated otherwise, the operating condi tions for the parameters in the following table are: v ddp = 3.3 v, t a = 25 o c table 33 power supply parameters parameter symbol values unit note / test condition min. typ. max. active supply current 1)6) peripherals enabled frequency: f cpu / f periph / f ccu in mhz i ddpa cc ? ? ? ? ? ? ? ? ? ? i ddpa cc ? ? ? ? f cpu / f periph / f ccu in mhz i ddpd cc ? ? i ddph cc ? ? v bat =3.3v ? ? v bat =2.4v ? ? v bat =2.0v hibernate supply current rtc off 4) i ddph cc ? ? v bat =3.3v ? ? v bat =2.4v ? ? v bat =2.0v subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 71 v0.7, 2015-10 worst case active supply current 5) i ddpa cc ?? v ddp =3.6v, t j =150 o c v dda power supply current i dda cc ??? i ddp current at porst low i ddp_porst cc ? v ddp =3.3v, t j =25 o c ? v ddp =3.6v, t j =150 o c power dissipation p diss cc ?? v ddp =3.6v, t j =150 o c wake-up time from sleep to active mode t ssa cc ? ? ??? section 3.2.9 wake-up time from hibernate mode ??? section 3.3.2 1) cpu executing code from flash, all peripherals idle. 2) cpu in sleep, peripherals disabled, after wake-up code execution from ram. 3) osc_ulp operating with external crystal on rtc_xtal 4) osc_ulp off, hibernate domain operating with osc_si clock 5) test power loop: f sys = 144 mhz, cpu executing benchmark code from flash, all ccus in 100khz timer mode, all adc groups in continuous conversion mode, usics as spi in internal loop-back mode, can in 500khz internal loop-back mode, interrupt triggered dm a block transfers to parity protected rams and fce, dts measurements and fpu calculations. the power consumption of each custom er application will most probably be lower than this value, but must be evaluated separately. 6) i ddp decreases typically by approximately 8.5 ma when f sys decreases by 10 mhz, at constant t j 7) sum of currents of all active converters (adc and dac) table 33 power supply parameters parameter symbol values unit note / test condition min. typ. max. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 72 v0.7, 2015-10 3.2.9 flash memory parameters note: these parameters are not subject to production test, but verified by design and/or characterization. table 34 flash memory parameters parameter symbol values unit note / test condition min. typ. max. erase time per 256 kbyte sector t erp cc ? t erp cc ? t erp cc ? t prp cc ? t fl_ersusp cc ?? t fl_margin del cc 10 ?? t wu cc ?? t a cc 22 ?? f cpu < t a wait states must be configured 2) data retention time, physical sector 3)4) t ret cc 20 ?? t retl cc 20 ?? t rtu cc 20 ?? n eps4 cc 10000 ?? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 73 v0.7, 2015-10 1) in case the program verify feature detects weak bits, these bits will be programmed once more. the reprogramming takes an additional time of 5.5 ms. 2) the following formula applies to the wait state configuration: fcon.wspflash f cpu ) t a . 3) storage and inactive time included. 4) values given are valid for an average weighted junction temperature of t j = 110c. 5) only valid with robust eeprom emulation algorithm, equa lly cycling the logical sectors. for more details see the reference manual. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 74 v0.7, 2015-10 3.3 ac parameters 3.3.1 testing waveforms figure 22 rise/fall time parameters figure 23 testing waveform, output delay figure 24 testing waveform, output high impedance ac_rise-fall-times.vsd 10 % 90 % v ss v ddp t r t f 10% 90 % ac_testpoints.vsd v ddp / 2 v ddp / 2 v ddp v ss test points ac_highimp.vsd v load + 0.1v timing reference points v load -0.1v v oh -0.1v v ol + 0.1v subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 75 v0.7, 2015-10 3.3.2 power-up and supply monitoring porst is always asserted when v ddp and/or v ddc violate the respective thresholds. note: these parameters are not subject to production test, but verified by design and/or characterization. figure 25 porst circuit table 35 supply monitoring parameters parameter symbol values unit note / test condition min. typ. max. digital supply voltage reset threshold v por cc 2.79 1) 1) minimum threshold for reset assertion. ? v pv cc ?? v ddp voltage to ensure defined pad states v ddppa cc ? ? t pr sr ?? t ssw cc ? v ddc ramp up time t vcr cc ? ? v por or v pv v ddp porst gnd poreset v ddp gnd xmc4000 r porst (optional) external reset trigger supply monitoring i ppd subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 76 v0.7, 2015-10 figure 26 power-up behavior 3.3.3 power sequencing while starting up and shutting down as well as when switching power modes of the system it is important to limi t the current load steps. a typi cal cause for such load steps is changing the cpu frequency f cpu . load steps exceeding the below defined values may cause a power on reset triggered by the supply monitor. note: these parameters are not subject to production test, but verified by design and/or characterization. 2) maximum threshold for reset deassertion. 3) the v ddp monitoring has a typical hysteresis of v porhys =180mv. 4) if t pr is not met, low spikes on porst may be seen during start up (e.g. reset pulses generated by the supply monitoring due to a slow ramping v ddp ). as programmed v por v pv v ddp v ddc pads porst v d d ppa undefined high - impedance or pull - device active 3.3 v 1.3 v t ssw t vcr t pr subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 77 v0.7, 2015-10 positive load step examples system assumptions: f cpu = f sys , target frequency f cpu = 144 mhz, main pll f vco = 288 mhz, stepping done by k2 divider, t plss between individual steps: 24 mhz - 48 mhz - 72 mhz - 96 mhz - 144 mhz (k2 steps 12 - 6 - 4 - 3 - 2) 24 mhz - 48 mhz - 96 mhz - 144 mhz (k2 steps 12 - 6 - 3 - 2) 24 mhz - 72 mhz - 144 mhz (k2 steps 12 - 4 - 2) table 36 power sequencing parameters parameter symbol values unit note / test condition min. typ. max. positive load step current i pls sr - ? v ddp t i nls sr - ? v ddp t v ddc voltage over- / undershoot from load step v ls cc - ? t plss sr 50 ? t nlss sr 100 ? v ddc c ext sr - 10 - c = 100 nf capacitor on each v ddc pin subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 78 v0.7, 2015-10 3.3.4 phase locked loop (pll) characteristics note: these parameters are not subject to production test, but verified by design and/or characterization. main and usb pll table 37 pll parameters parameter symbol values unit note / test condition min. typ. max. accumulated jitter d p cc ?? f sys =144mhz duty cycle 1) 1) 50% for even k2 divider values, 50(10/k2) for odd k2 divider values. d dc cc 46 50 54 % low pulse to total period, assuming an ideal input clock source pll base frequency f pllbase cc 30 ? f ref cc 4 ? f vco cc 260 ? t l cc ?? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 79 v0.7, 2015-10 3.3.5 internal clock source characteristics note: these parameters are not subject to production test, but verified by design and/or characterization. fast internal clock source table 38 fast internal clock parameters parameter symbol values unit note / test condition min. typ. max. nominal frequency f ofinc cc ? ? ? ? f ofi cc -0.5 ? v ddp supply voltage. -15 ? v ddp =3.3v -25 ? v ddp =3.3v -7 ? v ddp v ddp voltage induce an additional error to the uncalibrated and/or factory calibrated oscillator frequency. start-up time t ofis cc ? ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 80 v0.7, 2015-10 slow internal clock source table 39 slow internal clock parameters parameter symbol values unit note / test condition min. typ. max. nominal frequency f osi cc ? ? f osi cc -4 ? v bat = const. 0c t a ? v bat = const. t a < t a > ? v bat , t a =25c -10 ? v bat <2.4v, t a =25c start-up time t osis cc ? ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 81 v0.7, 2015-10 3.3.6 jtag interface timing the following parameters are applicable for communication through the jtag debug interface. the jtag module is fu lly compliant with ieee1149.1-2000. note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply. table 40 jtag interface timing parameters parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr 25 ? ? ns tck high time t 2 sr 10 ? ? ns tck low time t 3 sr 10 ? ? ns tck clock rise time t 4 sr??4ns tck clock fall time t 5 sr??4ns tdi/tms setup to tck rising edge t 6 sr6??ns tdi/tms hold after tck rising edge t 7 sr6??ns tdo valid after tck falling edge 1) (propagation delay) 1) the falling edge on tck is used to generate the tdo timing. t 8 cc??13nsc l =50pf 3??nsc l =20pf tdo hold after tck falling edge 1) t 18 cc2??ns tdo high imped. to valid from tck falling edge 1)2) 2) the setup time for tdo is given implicitly by the tck cycle time. t 9 cc??14nsc l =50pf tdo valid to high imped. from tck falling edge 1) t 10 cc ? ? 13.5 ns c l =50pf subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 82 v0.7, 2015-10 figure 27 test clock timing (tck) figure 28 jtag timing jtag_tck .vsd 0.9 v ddp 0.5 v ddp tck t 1 t 2 0.1 v ddp t 3 t 5 t 4 jtag_io.vsd t 6 t 7 t 6 t 7 t 9 t 8 t 10 tck tms tdi tdo t 18 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 83 v0.7, 2015-10 3.3.7 serial wire debug port (sw-dp) timing the following parameters are applicable for communication through the sw-dp interface. note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply. figure 29 swd timing table 41 swd interface timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. swdclk clock period t sc sr 25 ? ? ns c l =30pf 40 ? ? ns c l =50pf swdclk high time t 1 sr 10 ? 500000 ns swdclk low time t 2 sr 10 ? 500000 ns swdio input setup to swdclk rising edge t 3 sr 6 ? ? ns swdio input hold after swdclk rising edge t 4 sr 6 ? ? ns swdio output valid time after swdclk rising edge t 5 cc ? ? 17 ns c l =50pf ? ? 13 ns c l =30pf swdio output hold time from swdclk rising edge t 6 cc 3 ? ? ns swdclk swdio (output) t 1 t 2 t 6 t 5 t sc swdio (input) t 3 t 4 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 84 v0.7, 2015-10 3.3.8 embedded trace macro cell (etm) timing the data timing refers to the active clock edge. the xmc4[78]00 etm uses the half-rate clocking mode. in this mode both, the rising and falling clock edges are active clock edges. note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply, with c l 15 pf. figure 30 etm clock timing figure 31 etm data timing table 42 etm interface timing parameters parameter symbol values unit note / test condition min. typ. max. traceclk period t 1 cc 13.8 ? ? ns ? traceclk high time t 2 cc 2 ? ? ns ? traceclk low time t 3 cc 2 ? ? ns ? traceclk and tracedata rise time t 4 cc ? ? 3 ns ? traceclk and tracedata fall time t 5 cc ? ? 3 ns ? tracedata output valid time t 6 cc -2 ? 3 ns ? traceclk t 1 t 2 t 3 t 4 t 5 traceclk tracedata t 6 t 6 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 85 v0.7, 2015-10 3.3.9 peripheral timing 3.3.9.1 delta-sigma demodula tor digital in terface timing the following parameters are applicable for th e digital interface of the delta-sigma demodulator (dsd). the data timing is relative to the active clock edge. depending on the operation mode of the connected modulator that can be the rising and falling clock edge. note: these parameters are not subject to production test, but verified by design and/or characterization. table 43 dsd interfa ce timing parameters parameter symbol values unit note / test condition min. typ. max. mclk period in master mode t 1 cc 33.3 ? ? ns t 1 t periph 1) 1) t periph =1/ f periph mclk high time in master mode t 2 cc 9 ? ? ns t 2 > t periph 1) mclk low time in master mode t 3 cc 9 ? ? ns t 3 > t periph 1) mclk period in slave mode t 1 sr 33.3 ? ? ns t 1 t periph 1) mclk high time in slave mode t 2 sr t periph ??ns 1) mclk low time in slave mode t 3 sr t periph ??ns 1) din input setup time to the active clock edge t 4 sr t periph +4 ??ns 1) din input hold time from the active clock edge t 5 sr t periph +3 ??ns 1) subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 86 v0.7, 2015-10 figure 32 dsd data timing 3.3.9.2 synchronous serial interface (usic ssc) timing the following parameters are applicable for a usic channel operated in ssc mode. note: these parameters are not subject to production test, but verified by design and/or characterization. table 44 usic ssc master mode timing parameter symbol values unit note / test condition min. typ. max. sclkout master clock period t clk cc 33.3 ?? t 1 cc t pb - 6.5 1) 1) t pb = 1 / f pb ?? t 2 cc t pb - 8.5 1) ?? t 3 cc -6 ? t 4 sr 23 ?? t 5 sr 1 ?? t 2 t 3 t 5 t 4 t 1 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 87 v0.7, 2015-10 table 45 usic ssc slave mode timing parameter symbol values unit note / test condition min. typ. max. dx1 slave clock period t clk sr 66.6 ?? t 10 sr 3 ?? t 11 sr 4 ?? t 12 sr 6 ?? t 13 sr 4 ?? t 14 cc 0 ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 88 v0.7, 2015-10 figure 33 usic - ssc master/slave mode timing note: this timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted. t 2 t 1 usic_ssc_tmgx.vsd clock output sclkout data output dout[3:0] t 3 t 3 t 5 data valid t 4 fi rs t trans mi t edge data input dx0/dx[5:3] select output selox active master mode timing slave mode timing t 11 t 10 clock input dx1 data output dout[3:0] t 14 t 14 data valid data input dx0/dx[5:3] select input dx2 active t 13 t 12 transmit edge: with this clock edge , transmit data is shifted to transmit data output . receive edge: with this clock edge , receive data at receive data input is latched . receive edge last receive edge inactive inactive transmit edge inactive inactive first transmit edge receive edge transmit edge last receive edge t 5 data valid t 4 data valid t 12 t 13 drawn for brgh .sclkcfg = 00 b . also valid for for sclkcfg = 01 b with inverted sclkout signal. subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 89 v0.7, 2015-10 3.3.9.3 inter-ic (iic) interface timing the following parameters are applicable fo r a usic channel operated in iic mode. note: these parameters are not subject to production test, but verified by design and/or characterization. table 46 usic iic standard mode timing 1) 1) due to the wired-and configuration of an iic bus system, the port drivers of the scl and sda signal lines need to operate in open-drain mode. the high level on these lines must be held by an external pull-up device, approximalely 10 kohm for operation at 100 kbit/s, approximately 2 kohm for operation at 400 kbit/s. parameter symbol values unit note / test condition min. typ. max. fall time of both sda and scl t 1 cc/sr --300ns rise time of both sda and scl t 2 cc/sr - - 1000 ns data hold time t 3 cc/sr 0- - s data set-up time t 4 cc/sr 250 - - ns low period of scl clock t 5 cc/sr 4.7 - - s high period of scl clock t 6 cc/sr 4.0 - - s hold time for (repeated) start condition t 7 cc/sr 4.0 - - s set-up time for repeated start condition t 8 cc/sr 4.7 - - s set-up time for stop condition t 9 cc/sr 4.0 - - s bus free time between a stop and start condition t 10 cc/sr 4.7 - - s capacitive load for each bus line c b sr - - 400 pf subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 90 v0.7, 2015-10 table 47 usic iic fast mode timing 1) 1) due to the wired-and configuration of an iic bus system, the port drivers of the scl and sda signal lines need to operate in open-drain mode. the high level on these lines must be held by an external pull-up device, approximalely 10 kohm for operation at 100 kbit/s, approximately 2 kohm for operation at 400 kbit/s. parameter symbol values unit note / test condition min. typ. max. fall time of both sda and scl t 1 cc/sr 20 + 0.1*c b 2) 2) c b refers to the total capacitance of one bus line in pf. - 300 ns rise time of both sda and scl t 2 cc/sr 20 + 0.1*c b 2) - 300 ns data hold time t 3 cc/sr 0- - s data set-up time t 4 cc/sr 100 - - ns low period of scl clock t 5 cc/sr 1.3 - - s high period of scl clock t 6 cc/sr 0.6 - - s hold time for (repeated) start condition t 7 cc/sr 0.6 - - s set-up time for repeated start condition t 8 cc/sr 0.6 - - s set-up time for stop condition t 9 cc/sr 0.6 - - s bus free time between a stop and start condition t 10 cc/sr 1.3 - - s capacitive load for each bus line c b sr - - 400 pf subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 91 v0.7, 2015-10 figure 34 usic iic stand and fast mode timing 3.3.9.4 inter-ic sound (iis) interface timing the following parameters are applicable for a usic channel operated in iis mode. note: these parameters are not subject to production test, but verified by design and/or characterization. table 48 usic iis master transmitter timing parameter symbol values unit note / test condition min. typ. max. clock period t 1 cc 33.3 ?? t 2 cc 0.35 x t 1min ?? t 3 cc 0.35 x t 1min ?? t 4 cc 0 ?? t 5 cc ?? t 1min ns scl sda scl sda t 1 t 2 t 1 t 2 t 10 t 9 t 7 t 8 t 7 t 3 t 4 t 5 t 6 ps sr s 70% 30 % 9 th clock 9 th clock subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 92 v0.7, 2015-10 figure 35 usic iis master transmitter timing figure 36 usic iis slave receiver timing table 49 usic iis slave receiver timing parameter symbol values unit note / test condition min. typ. max. clock period t 6 sr 66.6 ?? t 7 sr 0.35 x t 6min ?? t 8 sr 0.35 x t 6min ?? t 9 sr 0.2 x t 6min ?? t 10 sr 0 ?? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 93 v0.7, 2015-10 3.3.9.5 sdmmc interface timing note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply, total external capacitive load c l = 40 pf. ac timing specifications (full-speed mode) table 50 sdmmc timing for full-speed mode parameter symbol values unit note/ test condition min. max. clock frequency in full speed transfer mode (1/ t pp ) f pp cc 0 24 mhz clock cycle in full speed transfer mode t pp cc 40 ? t wl cc 10 ? t wh cc 10 ? t tlh cc ? t thl cc ? t isu_f sr 2 ? t ih_f sr 2 ? t odly_f cc ? t oh_f cc 0 ? table 51 sd card bus timing for full-speed mode 1) parameter symbol values unit note/ test condition min. max. sd card input setup time t isu 5 ? t ih 5 ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 94 v0.7, 2015-10 full-speed output path (write) figure 37 full-speed output path full-speed write meeting setup (maximum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. no clock delay: (1) sd card output valid time t odly ? t oh 0 ? table 51 sd card bus timing for full-speed mode 1) (cont?d) parameter symbol values unit note/ test condition min. max. sd clock at host pin sd clock at card pin output at host pins output at card pins t pp (clock cycle ) driving edge sampling edge t wl t clk_delay output valid time: t odly_h output hold time: t oh_h t data _delay + t tap_delay t isu t ih t odly_f t data_delay t tap_delay t isu +++ t wl < subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 95 v0.7, 2015-10 with clock delay: (2) (3) the data can be delayed versus clock up to 5 ns in ideal case of t wl = 20 ns. full-speed write meeting hold (minimum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. (4) the clock can be delayed versus data up to 18. 2 ns (external delay line) in ideal case of t wl = 20 ns, with maximum t tap_delay = 3.2 ns programmed. t odly_f t data_delay t tap_delay t isu +++ t wl t clk_delay + < t data_delay t tap_delay t wl ++ t pp t clk_delay t isu ? t odly_f ? + < t data_delay t tap_delay 20 ++40 t clk_delay 5 ?10 ? + < t data_delay 5 t clk_delay t tap_delay ? + < t clk_delay t wl t oh_f t data_delay t tap_delay t ih ? ++ + < t clk_delay 20 t data_delay t tap_delay 5? ++ < t data_delay 15 t clk_delay t tap_delay ++ < subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 96 v0.7, 2015-10 full-speed inpu t path (read) figure 38 full-speed input path full-speed read meeting setup (maximum delay) the following equations show how to calcul ate the allowed combined propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. (5) the data + clock delay can be up to 4 ns for a 40 ns clock cycle. sd clock at host pin sd clock at card pin output at host pins output at card pins t pp (clock cycle ) driving edge sampling edge t clk_delay t odly t oh t data_delay + t tap_delay t ih _h t isu_h t clk_delay t data_delay t tap_delay t odly t isu_f + + + + 0,5 t pp < t clk_delay t data_delay + 0,5 t pp t odly t isu_f ?? t tap_delay ? < t clk_delay t data_delay + 20142 ?? t tap_delay ? < t clk_delay t data_delay +4 t tap_delay ? < subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 97 v0.7, 2015-10 full-speed read meeting hold (minimum delay) the following equations show how to calcul ate the allowed combined propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. (6) the data + clock delay must be greater than 2 ns if t tap_delay is not used. if the t tap_delay is programmed to at least 2 ns, t he data + clock delay must be greater than 0 ns (or less). this is always fulfilled. ac timing specifications (high-speed mode) table 52 sdmmc timing for high-speed mode parameter symbol values unit note/ test condition min. max. clock frequency in high speed transfer mode (1/ t pp ) f pp cc 0 48 mhz clock cycle in high speed transfer mode t pp cc 20 ? t wl cc 7 ? t wh cc 7 ? t tlh cc ? t thl cc ? t isu_h sr 2 ? t ih_h sr 2 ? t odly_h cc ? t oh_h cc 2 ? t clk_delay t oh t data_delay t tap_delay t ih_f > ++ + t clk_delay t data_delay t ih_f t oh ? t tap_delay ? > + t clk_delay t data_delay 2 t tap_delay ? > + subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 98 v0.7, 2015-10 high-speed output path (write) figure 39 high-speed output path high-speed write meetin g setup (maximum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. table 53 sd card bus timing for high-speed mode 1) 1) reference card timing values for calculation examples . not subject to production test and not characterized. parameter symbol values unit note/ test condition min. max. sd card input setup time t isu 6 ? t ih 2 ? t odly ? t oh 2.5 ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 99 v0.7, 2015-10 no clock delay: (7) with clock delay: (8) (9) the data delay is less than the clock delay by at least 10 ns in the ideal case where t wl = 10 ns. high-speed write meeting hold (minimum delay) the following equations show how to calculate the allowed skew range between the sd_clk and sd_dat/cmd signals on the pcb. (10) the clock can be delayed versus data up to 13. 2 ns (external delay line) in ideal case of t wl = 10 ns, with maximum t tap_delay = 3.2 ns programmed. t odly_h t data_delay t tap_delay t isu +++ t wl < t odly_h t data_delay t tap_delay t isu +++ t wl t clk_delay + < t data_delay t tap_delay t clk_delay ? + t wl t isu ? t odly_h ? < t data_delay t clk_delay ? t wl t isu ? t odly_h ? t tap_delay ? < t data_delay t clk_delay ?1 0 6 ?14 ? t tap_delay ? < t data_delay t clk_delay ?1 0 ? t tap_delay ? < t clk_delay t wl t oh_h t data_delay t tap_delay t ih ? ++ + < t clk_delay t data_delay ? t wl t oh_h t tap_delay t ih ? ++ < t clk_delay t data_delay ?1 0 2 t tap_delay 2? ++ < t clk_delay t data_delay ?1 0 t tap_delay + < subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 100 v0.7, 2015-10 high-speed input path (read) figure 40 high-speed input path high-speed read meeting setup (maximum delay) the following equations show how to calcul ate the allowed combined propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. (11) the data + clock delay can be up to 4 ns for a 20 ns clock cycle. sd clock at host pin sd clock at card pin output at host pins output at card pins t pp (clock cycle) driving edge sampling edge t clk_delay t odly t oh t data_delay + t tap_delay t ih _h t isu_h t clk_delay t data_delay t tap_delay t odly t isu_h ++++ t pp < t clk_delay t data_delay + t pp t odly t isu_h ?? t tap_delay ? < t clk_delay t data_delay + 20142 ?? t tap_delay ? < t clk_delay t data_delay +4 t tap_delay ? < subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 101 v0.7, 2015-10 high-speed read meeting hold (minimum delay) the following equations show how to calcul ate the allowed combined propagation delay range of the sd_clk and sd_dat/cmd signals on the pcb. (12) the data + clock delay must be greater than -0.5 ns for a 20 ns clock cycle. this is always fulfilled. 3.3.10 ebu timing note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply, with class a2 pins and c l = 16 pf. 3.3.10.1 ebu asynchronous timing note: for each timing, the accumulated pll jitter must be added separately. table 54 common timing parameters for all asynchronous timings parameter sym bol limit values unit edge setting min. max. pulse width deviation from the ideal programmed width due to the a2 pad asymmetry, strong driver mode, rise delay - fall delay. c l = 16 pf. cc t a -1 1.5 ns sharp -2 1 medium ad(24:16) output delay to adv rising edge, multiplexed read / write cc t 13 -5.5 2 ? ad(24:16) output delay cc t 14 -5.5 2 ? t clk_delay t oh t data_delay t tap_delay t ih_h > > > > subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 102 v0.7, 2015-10 read timing table 55 asynchronous read timing, multiplexed and demultiplexed parameter symbol li mit values unit min. max. a(24:16) output delay to rd rising edge, deviation from the ideal programmed value. cc t 0 -2.5 2.5 ns a(24:16) output delay cc t 1 -2.5 2.5 cs rising edge cc t 2 -2 2.5 adv rising edge cc t 3 -1.5 4.5 bc rising edge cc t 4 -2.5 2.5 wait input setup sr t 5 12 ? wait input hold sr t 6 0? data input setup sr t 7 12 ? data input hold sr t 8 0? rd / w r output delay cc t 9 -2.5 1.5 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 103 v0.7, 2015-10 multiplexed read timing figure 41 multiplexed read access t 8 next addr. ebu_muxrd_async.vsd ad[31:0] 2) data in a[max:16] 1) t 2 t a t a t a t a t 4 t 5 t 6 t a t 13 t 14 t 7 t 9 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 t 1 t 0 pv + pv + pv + pv + pv + t 3 pv + pv + pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (corresponding bitfield values) command delay phase 0...7 1) for 16-bit mux and twin 16-bit mux only 2) * 16-bit mux: - address a[15:0], data d[15:0] on pins ad[15:0] only * twin 16-bit mux: - address a[15:0] on pins ad[15:0] and ad[31:16] in parallel - data d[31:0] on pins ad[31:0] * 32-bit mux: - address a[24:0] on pins ad[24:0] - data d[31:0] on pins ad[31:0] address out valid address rd/wr bc[3:0] wait rd adv cs[3:0] cscomb subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 104 v0.7, 2015-10 demultiplexed read timing figure 42 demultiplexed read access t 8 next addr. ebu_demuxrd_async.vsd d[15:0] 2) data in a[max:0] 1) t 2 t a t a t a t a t 4 t 5 t 6 t a t 7 t 9 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 t 1 t 0 pv + pv + pv + pv + pv + t 3 pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (corresponding bitfield values) 1) address a[max:16] on pins a[max:16], address a[15:0] on pins ad[31:16] 2) data d[15:0] on pins ad[15:0] valid address rd/wr bc[3:0] wait rd adv cs[3:0] cscomb subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 105 v0.7, 2015-10 write timing table 56 asynchronous write timing, multiplexed and demultiplexed parameter symbol limit values unit min. max. a(24:0) output delay to rd/wr rising edge, deviation from the ideal programmed value. cc t 30 -2.5 2.5 ns a(24:0) output delay cc t 31 -2.5 2.5 cs rising edge cc t 32 -2 2 adv rising edge cc t 33 -2 4.5 bc rising edge cc t 34 -2.5 2 wait input setup sr t 35 12 ? wait input hold sr t 36 0? data output delay cc t 37 -5.5 2 data output delay cc t 38 -5.5 2 rd / w r output delay cc t 39 -2.5 1.5 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 106 v0.7, 2015-10 multiplexed write timing figure 43 multiplexed write access t 34 next addr. ebu_muxwr_async.vsd ad[31:0] 2) data out a[max:16] 1) t a t a t a t a t 35 t 36 t a t 13 t 14 pv + t 37 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase 1...15 0...15 duration limits in ebu_clk cycles 0...15 1...15 t 31 t 30 pv + pv + pv + pv + pv + t 33 pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (corresponding bitfield values) data hold phase 1...31 1) for 16-bit mux and twin 16-bit mux only 2) * 16-bit mux: - address a[15:0], data d[15:0] on pins ad[15:0] only * twin 16-bit mux: - address a[15:0] on pins ad[15:0] and ad[31:16] in parallel - data d[31:0] on pins ad[31:0] * 32-bit mux: - address a[24:0] on pins ad[24:0] - data d[31:0] on pins ad[31:0] t 32 pv + t 38 pv + address out 0...15 rd/wr bc[3:0] wait rd adv cs[3:0] cscomb valid address t 39 pv + subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 107 v0.7, 2015-10 demultiplexed write timing figure 44 demultiplexed write access t 34 next addr. ebu_demuxwr_async.vsd d[15:0] 2) data out a[max:0] 1) t a t a t a t a t 35 t 36 t a pv + t 37 t 39 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase 1...15 0...15 duration limits in ebu_clk cycles 0...15 1...15 t 31 t 30 pv + pv + pv + pv + pv + t 33 pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (corresponding bitfield values) data hold phase 1...31 t 32 pv + t 38 pv + 0...15 1) address a[max:16] on pins a[max:16], address a[15:0] on pins ad[31:16] 2) data d[15:0] on pins ad[15:0] rd/wr bc[3:0] wait rd adv cs[3:0] cscomb valid address subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 108 v0.7, 2015-10 3.3.10.2 ebu burst mode access timing note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply, with class a2 pins and c l = 16 pf. table 57 ebu burst mode read / write access timing parameters parameter symbol values unit note / test condition min. typ. max. output delay from bfclko rising edge t 10 cc -2 ? 2 ns ? rd and rd/wr active/inactive after bfclko active edge 1) 1) an active edge can be a rising or falling edge, depending on the settings of bits bfcon.ebse / ecse and the clock divider ratio. negative minimum values for these parameters mean that the last data read during a burst may be corrupted. however, with clock feedback enabled, this value is an oversampling not required for the internal bus transaction, and will be discarded. t 12 cc -2 ? 2 ns ? cs x output delay from bfclko active edge 1) t 21 cc -2.5 ? 1.5 ns ? adv active/inactive after bfclko active edge 2) 2) this parameter is valid for busconx.ebse = 1 and busapx.extclk = 00 b . for busconx.ebse = 1 and other values of busapx.extcl k, adv and baa will be delayed by 1/2 of the internal bus clock period t cpu = 1 / f cpu . for busconx. ebse = 0 and busapx.extclk = 11 b , add 2 internal bus clock periods. for busconx. ebse = 0 and other values of busapx.extclk, add 1 internal bus clock period. t 22 cc -2 ? 2 ns ? baa active/inactive after bfclko active edge 2) t 22a cc -2.5 ? 1.5 ns ? data setup to bfclki rising edge 3) t 23 sr 3 ? ? ns ? data hold from bfclki rising edge 3) t 24 sr 0 ? ? ns ? wait setup (low or high) to bfclki rising edge 3) t 25 sr 3 ? ? ns ? wait hold (low or high) from bfclki rising edge 3) t 26 sr 0 ? ? ns ? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 109 v0.7, 2015-10 figure 45 ebu burst mode read / write access timing 3) if the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as for asynchronous access. thus, t 5 , t 6 , t 7 and t 8 from the asynchronous timing apply. ebu_burstrdwr.vsd t 10 bfclki bfclko 1) a[max :0 ] t 22 address p hase (s) command phase(s) burst phase(s) recovery phase(s) next addr. phase(s) t 22 t 21 next addr . d[31:0] (32-bit) t 12 t 12 t 24 d[15:0] (16-bit) t 22a burst phase (s) t 22a t 10 t 22 t 23 t 24 t 23 t 26 t 25 output delays are always referenced to bclko . the reference clock for input characteristics depends on bit ebu _bfcon.fdbken. ebu_bfcon.fdbken = 0: bfclko is the input reference clock . ebu_bfcon.fdbken = 1: bfclki is the input reference clock (ebu clock feedback enabled ). 1) b urst start a ddress t 21 t 21 data (addr+0) data (addr+4) data (addr+2) data (addr+0) adv rd rd/wr cs[3:0] cscomb baa wait subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 110 v0.7, 2015-10 3.3.10.3 ebu arbitration signal timing note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply. figure 46 ebu arbitration signal timing table 58 ebu arbitration signal timing parameters parameter symbol values unit note / test cond ition min. typ. max. output delay from bfclko rising edge t 1 cc ? ? 16 ns c l = 50 pf data setup to bfclko falling edge t 2 sr 11 ? ? ns ? data hold from bfclko falling edge t 3 sr 2 ? ? ns ? t 2 t 2 ebu_arb .vsd bfclko t 3 t 1 t 1 t 1 t 1 hlda output breq output bfclko t 3 hold input hlda input subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 111 v0.7, 2015-10 3.3.10.4 ebu sdram access timing note: these parameters are not subject to production test, but verified by design and/or characterization. note: operating conditions apply, with class a2 pins and c l = 16 pf. note: with ebu_clc.sync = 1 b frequency must be limited to f cpu = 120 mhz. figure 47 ebu sdram access clkout timing table 59 ebu sdram access sdclko signal timing parameters parameter symbol values unit note / test con dition min. typ. max. sdclko period t 1 cc 12.5 ? ? ns ? sdclko high time t 2 sr 5.5 ? ? ns ? sdclko low time t 3 sr 3.75 ? ? ns ? sdclko rise time t 4 sr ? ? 3.0 ns ? sdclko fall time t 5 sr ? ? 3.0 ns ? ebu_sdclko.vsd 0.9 v ddp 0.5 v ddp sdclko t 1 t 2 0.1 v ddp t 3 t 5 t 4 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 112 v0.7, 2015-10 table 60 ebu sdram access signal timing parameters parameter symbol limit values unit min. max. a(15:0) output valid from sdclko low-to-high transition cc t 6 ?9ns a(15:0) output hold cc t 7 3? cs(3:0) low cc t 8 ?9 cs(3:0) high cc t 9 3? ras low cc t 10 ?9 ras high sr t 11 3? cas low sr t 12 ?9 cas high cc t 13 3? rd/wr low cc t 14 ?9 rd/wr high cc t 15 3? bc(3:0) low cc t 16 ?9 bc(3:0) high cc t 17 3? d(15:0) output valid cc t 18 ?9 d(15:0) output hold cc t 19 3? cke output valid 1) 1) not depicted in the read and write access timing figures below. cc t 22 ?7 cke output hold 1) cc t 23 2? d(15:0) input hold sr t 21 3? d(15:0) input setup to sdclko low-to-high transition sr t 20 4? subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 113 v0.7, 2015-10 figure 48 ebu sdram read access timing t 21 row ebu_sdram-rd.vsd t 6 column t 7 t 12 t 13 t 16 t 17 t 20 data (0) data (n-1) d[15:0] 2) a[15 :0] 1) rd /wr b c[1 :0 ] cs [3 :0 ] cscomb ras cas 1) a ddress a[15 :0 ] on pins ad [31 :16 ] 2) data d[15:0] on pins ad[15:0] sdclko t 9 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 114 v0.7, 2015-10 figure 49 ebu sdram write access timing column t 19 row ebu_sdram- wr.vsd t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 data (0) data (n-1 ) d[15:0] 2) a[15 :0] 1) rd /wr b c[1 :0 ] cs [3 :0 ] cscomb ras cas 1) a ddress a[15 :0 ] on pins ad [31 :16 ] 2) data d[15:0] on pins ad[15:0] sdclko subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 115 v0.7, 2015-10 3.3.11 usb interface characteristics the universal serial bus (usb) interface is compliant to the usb rev. 2.0 specification and the otg specification rev. 1.3. high-speed mode is not supported. note: these parameters are not subject to production test, but verified by design and/or characterization. figure 50 usb signal timing table 61 usb timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. rise time t r cc 4 ? 20 ns c l =50pf fall time t f cc 4 ? 20 ns c l =50pf rise/fall time matching t r /t f cc 90 ? 111.11 % c l =50pf crossover voltage v crs cc 1.3 ? 2.0 v c l =50pf usb_rise-fall-times.vsd 10% 90 % d- d+ t r t f 10 % 90% v crs v ss subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 116 v0.7, 2015-10 3.3.12 ethernet interface (eth) characteristics for proper operation of the ethernet interface it is required that f sys note: these parameters are not subject to production test, but verified by design and/or characterization. 3.3.12.1 eth measurement reference points figure 51 eth measurement reference points eth_testpoints.vsd eth clock 1.4 v 1.4 v 2.0 v 0.8 v 2.0 v 0.8 v t r t f eth i/o subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 117 v0.7, 2015-10 3.3.12.2 eth management signal parameters (eth_mdc, eth_mdio) figure 52 eth management signal timing table 62 eth management signal timing parameters parameter symbol values unit note / test conditi on min. typ. max. eth_mdc period t 1 cc 400 ? ? ns c l =25pf eth_mdc high time t 2 cc 160 ? ? ns eth_mdc low time t 3 cc 160 ? ? ns eth_mdio setup time (output) t 4 cc 10 ? ? ns eth_mdio hold time (output) t 5 cc 10 ? ? ns eth_mdio data valid (input) t 6 sr 0 ? 300 ns eth_timing-mgmt.vsd eth_mdc eth_mdio (output) t 5 valid data t 4 valid data t 6 eth_mdio (input) eth_mdc eth_mdio sourced by sta: eth_mdio sourced by phy: eth_mdc t 1 t 3 t 2 subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 118 v0.7, 2015-10 3.3.12.3 eth mii parameters in the following, the parameters of the mi i (media independent interface) are described. figure 53 eth mii signal timing table 63 eth mii signal timing parameters parameter symbol values unit note / test condition min. typ. max. clock period, 10 mbps t 7 sr 400 ? ? ns c l =25pf clock high time, 10 mbps t 8 sr 140 ? 260 ns clock low time, 10 mbps t 9 sr 140 ? 260 ns clock period, 100 mbps t 7 sr 40 ? ? ns clock high time, 100 mbps t 8 sr 14 ? 26 ns clock low time, 100 mbps t 9 sr 14 ? 26 ns input setup time t 10 sr 10 ? ? ns input hold time t 11 sr 10 ? ? ns output valid time t 12 cc 0 ? 25 ns eth_timing-mii.vsd eth_mii_rx_clk eth_mii _txd[3:0] eth_mii_txen eth_mii_rxd[3:0] eth_mii_rx_dv eth_mii _rx_er eth_mii_tx_clk t 11 valid data t 10 valid data t 12 (sourced by sta ) ( sourced by phy ) t 7 t 9 t 8 eth_mii_rx_clk eth_mii_tx_clk subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 119 v0.7, 2015-10 3.3.12.4 eth rmii parameters in the following, the parameters of the rmii (reduced media independent interface) are described. figure 54 eth rmii signal timing table 64 eth rmii signal timing parameters parameter symbol values unit note / test condit ion min. typ. max. eth_rmii_ref_cl clock period t 13 sr 20 ? ? ns c l =25pf; 50 ppm eth_rmii_ref_cl clock high time t 14 sr 7 ? 13 ns c l =25pf eth_rmii_ref_cl clock low time t 15 sr 7 ? 13 ns eth_rmii_rxd[1:0], eth_rmii_crs setup time t 16 sr 4 ? ? ns eth_rmii_rxd[1:0], eth_rmii_crs hold time t 17 sr 2 ? ? ns eth_rmii_txd[1:0], eth_rmii_txen data valid t 18 cc 4 ? 15 ns eth_timing-rmii .vsd eth_rmii_ref_cl t 17 valid data t 16 valid data t 18 t 13 t 15 t 14 eth_rmii_ref_cl eth_rmii_ref_cl eth_rmii _rxd[1:0] eth_rmii _crs eth_rmii _txd[1:0] eth_rmii _txen (sourced by sta ) (sourced by phy ) valid data subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 120 v0.7, 2015-10 3.3.13 ethercat (ecat) characteristics 3.3.13.1 ecat measurement reference points figure 55 measurement reference points 3.3.13.2 eth management signal parameters (mclk, mdio) table 65 ecat management si gnal timing parameters parameter symbol values unit note / test conditi on min. typ. max. ecat_mclk period t mclk cc ? 400 ? ns ieee802.3 requirement (2.5 mhz) c l =25pf ecat_mclk high time t mclk_h cc 160 ? ? ns ecat_mclk low time t mclk_l cc 160 ? ? ns ecat_mdio setup time (output) t d_setup cc 10 ? ? ns ecat_mdio hold time (output) t d_hold cc 10 ? ? ns ecat_mdio data valid (input) t d_valid sr 0 ? 300 ns ecat_testpoints.vsd ecat clock 1.4 v 1.4 v 2.0 v 0.8 v 2.0 v 0.8 v t r t f ecat i/o subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 121 v0.7, 2015-10 figure 56 ecat management signal timing 3.3.13.3 mii timing tx characteristics table 66 eth mii tx signal timing parameters parameter symbol values unit note / test condition min. typ. max. phy_clk25, tx_clk period t tx_clk sr ?40?ns delay between phy clock source phy_clk25 and tx_clk output of the phy t phy_delay sr ? ? ? ns phy dependent ecat_timing-mgmt.vsd ecat_mclk ecat_mdio (output) valid data t d_setup valid data t d_valid ecat_mdio (input) ecat_mclk ecat_mdio sourced by sta: ecat_mdio sourced by phy: ecat_mclk t mclk t mclk_l t mclk_h t d_hold subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 122 v0.7, 2015-10 note: ecat0_conpx.tx_shift can be adjusted by displaying tx_clk of a phy and txen/txd[3:0] on an oscilloscope. txen/txd[3:0] is allowed to change between 0 ns and 25 ns after a rising edge of tx_clk (according to ieee802.3 ? check your phy?s documentation). configure tx_shift so that txen/txd[3:0] change near the middle of this range. it is sufficient to check just one of the txen/txd[3:0] signals, because they are nearly generated at the same time. figure 57 mii tx characteristics phy setup requirement: txen/txd[3:0] with respect to tx_clk t tx_setup sr 15 ? 0 ns phy dependent ieee802.3 limit is 15 ns phy hold requirement: txen/txd[3:0] with respect to tx_clk t tx_hold cc 0 ? 25 ns phy dependent ieee802.3 limit is 0 ns table 66 eth mii tx signal timing parameters (cont?d) parameter symbol values unit note / test condition min. typ. max. t phy_delady ecat_mii_txd[3:0] ecat_mii_txen valid data ecat_mii_tx_clk phy_clk25 t phy_tx_setup t phy_tx_hold tx_shift[1:0]=00 valid data valid data 10ns 20ns 30ns ecat_mii_txd[3:0] ecat_mii_txen tx_shift[1:0]=01 ecat_mii_txd[3:0] ecat_mii_txen tx_shift[1:0]=10 ecat_mii_txd[3:0] ecat_mii_txen tx_shift[1:0]=11 valid data fail: ? ? ? t tx_clk subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 123 v0.7, 2015-10 3.3.13.4 mii timing rx characteristics figure 58 mii rx characteristics table 67 eth mii rx signal timing parameters parameter symbol values unit note / test condition min. typ. max. rx_clk period t rx_clk sr ?40?nsc l =25pf, ieee802.3 requirement rx_dv/rx_dv/rxd[3:0] valid before rising edge of rx_clk t rx_setup sr 10 ? ? ns rx_dv/rx_dv/rxd[3:0] valid after rising edge of rx_clk t rx_hold sr 10 ? ? ns ecat_mii_rx_clk t rx_hold t rx_setup valid data ecat_mii_rxd[3:0] ecat_mii_rx_dv ecat_mii_rx_er t rx_clk subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family electrical parameters preliminary data sheet 124 v0.7, 2015-10 3.3.13.5 sync/latch timings note: sync0/1 pulse length are initially loaded by eeprom content adr 0x0002. the actual used value can be read back from register dc_pulse_len. figure 59 sync/latch timings table 68 sync/latch timings parameter symbol values unit note / test condition min. typ. max. sync0/1 t dc_sync_ jitter sr ? ? 11 + m 1) 1) additional delay form logic and pad, number is added after characterization ns latch0/1 t dc_latch sr 12 + n 2) 2) additional shaping delay, number is added after characterization ?? ns t dc_sync_jiiter sync0/1 latch0/1 t dc_latch t dc_latch subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family package and reliability preliminary data sheet 125 v0.7, 2015-10 4 package and reliability the xmc4[78]00 is a member of the xmc4000 family of microcontrollers. it is also compatible to a certain extent with me mbers of similar families or subfamilies. each package is optimized for the device it houses. therefore, there may be slight differences between packages of the same pi n-count but for different device types. in particular, the size of the exposed die pad may vary. if different device types are considered or planned for an applicati on, it must be ensured that the board layout fits all packages under consideration. 4.1 package parameters table 69 provides the thermal characteristics of the packages used in xmc4[78]00. note: for electrical reasons, it is required to connect the exposed pad to the board ground v ss , independent of emc and thermal requirements. 4.1.1 thermal considerations when operating the xmc4 [78]00 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. the maximum heat that can be dissipated dep ends on the package and its integration into the target board. the ?thermal resistance r p int + p iostat + p iodyn ) r p int = v ddp i ddp (switching current and leakage current). table 69 thermal characteristics of the packages parameter symbol limit values unit package types min. max. exposed die pad dimensions ex r subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family package and reliability preliminary data sheet 126 v0.7, 2015-10 the static external power consumption caus ed by the output drivers is defined as p iostat = v ddp - v oh ) i oh ) + v ol i ol ) the dynamic external power consumpt ion caused by the output drivers ( p iodyn ) depends on the capacitive load connected to the resp ective pins and their switching frequencies. if the total power di ssipation for a given system configur ation exceeds the defined limit, countermeasures must be taken to ensure proper system operation: ? reduce v ddp , if possible in the system ? reduce the system frequency ? reduce the number of output pins ? reduce the load on active output drivers 4.2 package outlines the availability of different packages fo r different devices types is listed in table 1 . the exposed die pad dimensions are listed in table 69 . figure 60 pg-lqfp-144-24 (plastic green low profile quad flat package) subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family package and reliability preliminary data sheet 127 v0.7, 2015-10 figure 61 pg-lqfp-100-25 (plastic green low profile quad flat package) pg-lqfp-100-24, -25-po v04 0.5 24 x 0.5 = 12 0.2 a-b 0.08 m c c d 100x 100x -0.03 +0.07 2) 1.6 max. 0.05 0.05 c 0.1 0.08 1.4 0.15 0.6 h a b index marking 1 100 d 14 1) 16 0.2 c a-b d 0.2 h a-b d 100x 4x 14 1) 16 bottom view 100 1 exposed diepad seating plane coplanarity stand off -0.037 +0.073 0.127 0...7 3) ex 3) ax 3) ey 3) ay 1) does not include plastic or metal protrusion of 0.25 max. per side 2) does not include dambar protrusion of 0.08 max. per side 3) refer table for exposed pad dimension details subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family package and reliability preliminary data sheet 128 v0.7, 2015-10 figure 62 pg-lfbga-196-2 (plastic green low profile fine pitch ball grid array) all dimensions in mm. you can find complete information about infineon packages, packing and marking in our infineon internet page ?packages?: http://www.infineon.com/packages subject to agreement on the use of product information
xmc4700 / xmc4800 xmc4000 family quality declarations preliminary data sheet 129 v0.7, 2015-10 5 quality declarations the qualification of the xmc4[78]00 is executed according to the jedec standard jesd47i. note: for automotive applications refer to the infineon automotive microcontrollers. table 70 quality parameters parameter symbol values unit note / test condition min. typ. max. operation lifetime t op cc 20 ?? t j v hbm sr ?? v cdm sr ?? msl cc ?? ? t sdr sr ?? subject to agreement on the use of product information
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